In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. We present experimental results from applying these algorithms to problems in logic design verification that demonstrate the practicality of our approach. Index Terms: Boolean functions, symbolic manipulation, binary decision diagrams, logic design verification 1.

Ordered Binary-Decision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD

Efficient manipulation of Boolean functions is an important component of many computer-aided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementation of the if-then-else (ITE) operator. A hash table is used to maintain a strong carwnical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory funcfion for the recursive ITE algorithm is implemented using a hash-based cache to decrease memory use. Memory function efficiency is improved by using rules that detect. when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and low-cost scheme for rec:ycling memory. Experimental results are given to demonstrate why various implementation trade-offs were made. These results indicate that the package described here is significantly faster and more memory-efficient than other ROBDD implementations described in the literature. 1

This is the nineteenth edition of a (usually) quarterly column that covers new developments in the theory of NP-completeness. The presentation is modeled on that used by M. R. Garey and myself in our book ‘‘Computers and Intractability: A Guide to the Theory of NP-Completeness,’ ’ W. H. Freeman & Co., New York, 1979 (hereinafter referred to as ‘‘[G&J]’’; previous columns will be referred to by their dates). A background equivalent to that provided by [G&J] is assumed, and, when appropriate, cross-references will be given to that book and the list of problems (NP-complete and harder) presented there. Readers who have results they would like mentioned (NP-hardness, PSPACE-hardness, polynomial-time-solvability, etc.) or open problems they would like publicized, should

OBDD's are the state-of-the-art data structure for Boolean function manipulation since basic tasks of Boolean manipulation such as testing equivalence, satisfiability, or tautology, and performing single Boolean synthesis steps can be done efficiently. In the following we show that the efficient manipulation of OBDD's can be extended to a more general data structure, so-called FBDD's. In detail, the advantages of using FBDD's instead of OBDD's are ffl FBDD's are generally more (sometimes even exponentially more) succinct than OBDD's, ffl FBDD's provide, similarly to OBDD's, canonical representations of Boolean functions, and ffl in terms of FBDD's basic tasks of Boolean manipulation can be performed similarly efficient as in terms of OBDD's. The power of the FBDD-concept is demonstrated by showing that the verification of the benchmark circuit design for the hidden weighted bit function HWB proposed by Bryant can be carried out efficiently in terms of FBDD's while, for princip...

Abstract. A central issue in the solution of many computer aided design problems is to find concise representations for circuit designs and their functional specification. Recently, a restricted type of branching programs (OBDDs) proved to be extremely useful for representing Boolean functions for various CAD applications [Bry92]. Unfortunatelly, many circuits of practical interest provably require OBDD--representations of exponential size. In the following we systematically study the question up to what extend more concise BP-representations can be successfully used in symbolic Boolean manipulation, too. We prove, in very general settings, -- The frontier of efficient (deterministic) symbolic Boolean manipulation on the basis of BP--representations are read--once--only branching programs (BP1). -- The frontier of efficient probabilistic manipulation with BP--based data structures are parity read--once--only branching programs (\Phi-- BP1). Since BP1s and \Phi--BP1s are generally mor...

. The first result concerns branching programs having width (log n) O(1) . We give an \Omega\Gamma n log n= log log n) lower bound for the size of such branching programs computing almost any symmetric Boolean function and in particular the following explicit function: "the sum of the input variables is a quadratic residue mod p" where p is any given prime between n 1=4 and n 1=3 . This is a strengthening of previous nonlinear lower bounds obtained by Chandra, Furst, Lipton and by Pudl'ak. We mention that by iterating our method the result can be further strengthened to \Omega\Gamma n log n). The second result is a C n lower bound for read-once-only branching programs computing an explicit Boolean function. For n = \Gamma v 2 \Delta , the function computes the parity of the number of triangles in a graph on v vertices. This improves previous exp(c p n) lower bounds for other graph functions by Wegener and Z'ak. The result implies a linear lower bound for the space comp...

This note studies the learnability of ordered binary decision diagrams (obdds). We give a polynomial-time algorithm using membership and equivalence queries that finds the minimum obdd for the target respecting a given ordering. We also prove that both types of queries and the restriction to a given ordering are necessary if we want minimality in the output, unless P=NP. If learning has to occur with respect to the optimal variable ordering, polynomial-time learnability implies the approximability of two NP-hard optimization problems: the problem of finding the optimal variable ordering for a given obdd and the Optimal Linear Arrangement problem on graphs. 1 Introduction The representation of boolean functions as ordered binary decision diagrams (obdds) has received great attention recently. This representation has nice computational properties for fixed variable ordering such as the existence of a minimum canonical form and, efficient algorithms for elementary boolean operations, sat...

This work is settled in the area of complexity theory for restricted variants of branching programs. Today, branching programs can be considered one of the standard nonuniform models of computation. One reason for their popularity is that they allow to describe computations in an intuitively straightforward way and promise to be easier to analyze than the traditional models. In complexity theory, we are mainly interested in upper and lower bounds on the size of branching programs. Although proving superpolynomial lower bounds on the size of general branching programs still remains a challenging open problem, there has been considerable success in the study of lower bound techniques for various restricted variants, most notably perhaps read-once branching programs and OBDDs (ordered binary decision diagrams). Surprisingly, OBDDs have also turned out to be extremely useful in practical applications as a data structure for Boolean functions. So far, research has concentrated on determinis...

With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are generally inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal methods to guarantee the correctness of their designs. In this paper we survey some state-of-the-art techniques used to perform automatic verification of combinational circuits. We classify the current approaches for combinational verification into two categories: functional and structural. The functional methods consist of representing a circuit as a canonical decision diagram. Two circuits are equivalent if and only if their decision diagrams are equal. The structural methods consist of identifying related nodes in the circuit and using them to simplify the problem of verification. We briefly describe some of the methods in both the categories and discuss their merits and drawbacks.