In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. We present experimental results from applying these algorithms to problems in logic design verification that demonstrate the practicality of our approach. Index Terms: Boolean functions, symbolic manipulation, binary decision diagrams, logic design verification 1.

Ordered Binary-Decision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD

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In this paper we describe a data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations of Lee and Akers, but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms are quite efficient as long as the graphs being operated on do not grow too large. We present performance measurements obtained while applying these algorithms to problems in logic design verification.

. We investigate the use of oblivious, read-once decision graphs as structures for representing concepts over discrete domains, and present a bottom-up, hill-climbing algorithm for inferring these structures from labelled instances. The algorithm is robust with respect to irrelevant attributes, and experimental results show that it performs well on problems considered difficult for symbolic induction methods, such as the Monk's problems and parity. 1 Introduction Top down induction of decision trees [25, 24, 20] has been one of the principal induction methods for symbolic, supervised learning. The tree structure, which is used for representing the hypothesized target concept, suffers from some wellknown problems, most notably the replication problem and the fragmentation problem [23]. The replication problem forces duplication of subtrees in disjunctive concepts, such as (A B) (C D); the fragmentation problem causes partitioning of the data into fragments, when a high-arity attrib...

A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). And finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown. A partition method of outputs for parallel evaluation is also presented. A prototype has been developed by using RAM and FPGA.

This article describes the use of if-then-else dags for multi-level logic minimization. A new canonical form for if-then-else dags, analogous to Bryant's canonical form for binary decision diagrams (bdds), is introduced. Two-cuts are defined for binary decision diagrams, and a relationship is exhibited between general if-then-else expressions and the two-cuts of a bdd for the same function. The canonical form is based on representing the lowest non-trivial two-cut in the corresponding bdd, instead of the highest two-cut, as in Bryant's canonical form. The definitions of prime and irredundant expressions are extended to if-then-else dags.

We define the notion of a randomized branching program in the natural way similar to the definition of a randomized circuit. We exhibit an explicit function fn for which we prove that: 1) f n can be computed by polynomial size randomized read-once ordered branching program with a small one-sided error; 2) fn cannot be computed in polynomial size by deterministic readonce branching programs; 3) fn cannot be computed in polynomial size by deterministic read- k-times ordered branching program for k = o(n= log n) (the required deterministic size is exp \Gamma\Omega \Gamma n k \Delta\Delta ).

Spectral methods for analysis and design of digital logic circuits have been proposed and developed for several years. The widespread use of these techniques has suffered due to the associated computational complexity. This paper presents a new approach for the computation of spectral coefficients with polynomial complexity. Usually, the computation of the spectral coefficients involves the evaluation of inner products of vectors of exponential length. In the new approach, it is not necessary to compute inner products, rather, each spectral coefficient is expressed in terms of a measure of correlation between two Boolean functions. This formulation coupled with compact BDD representations of the functions reduces the overall complexity. Further, some computer aided design applications are presented that can make use of the new spectrum evaluation approach. In particular, the basis for a synthesis method that allows spectral coefficients to be computed in an iterative manner ...

... algorithm which incorporates coverage modeling into a BDD solution of a combinatorial model. BDDs, which do not use cutsets to generate system unreliability, may be used to nd exact solutions for extremely large systems. The DREDD algorithm takes advantage of the e ciency of the BDD solution approach and increases the accuracy of a combinatorial model by including consideration of (possibly) imperfect coverage. The usefulness of combinatorial models, long appreciated for their logical structure and concise representational form, is extended to include many fault tolerant systems previously thought to require more complicated analysis techniques in order to include coverage modeling. In this paper, the DREDD approach is presented and applied to the analysis of two sample systems, the F18 ight control system and a fault tolerant multistage interconnection network.