This paper demonstrates a first-order, linear power estimation model that uses performance counters to estimate run-time CPU and memory power consumption of the Intel PXA255 processor. Our model uses a set of power weights that map hardware performance counter values to processor and memory power consumption. Power weights are derived offline once per processor voltage and frequency configuration using parameter estimation techniques. They can be applied in a dynamic voltage/frequency scaling environment by setting six descriptive parameters. We have tested our model using a wide selection of benchmarks including SPEC2000, Java CDC and Java CLDC programming environments. The accuracy is quite good; average estimated power consumption is within 4 % of the measured average CPU power consumption. We believe such power estimation schemes can serve as a foundation for intelligent, poweraware embedded systems that dynamically adapt to the device’s power consumption.

As computer systems become ever more complex and power hungry, research on dynamic on-the-fly system management and adaptations receives increasing attention. Such research relies on recognizing and responding to patterns or phases in application execution, which has therefore become an important and widely-studied research area. While application phase analysis has received significant attention, much of this attention thus far has focused on simulation-based studies. In these cycle-level simulations without indeterministic operating system intervention, applications display behavior that is repeatable from phase to phase and from run to run. A natural question, therefore, concerns how these phases appear in real system runs, where interrupts and time variability can influence the timing and behavior of the program. Our work examines the phase behavior of applications running on real systems. The key goals of our work are to reliably discern and recover phase behavior in the face of application variability stemming from real system effects and time sampling. We propose a set of new, “transitionbased” phase detection techniques. Our techniques can detect repeatable workload phase information from timevarying, real system measurements with less than 5 % false alarm probabilities. In comparison to previous value-based detection methods, our transition-based techniques achieve on average 6X higher recurrent phase detection efficiency under real system variability. 1

As the market for mobile architectures continues its rapid growth, it has become increasingly important to understand and optimize the power consumption of these battery-driven devices. While energy consumption has been heavily explored, there is one critical factor that is often overlooked – the end user. Ultimately, the energy consumption of a mobile architecture is defined by user activity. In this paper, we study mobile architectures in their natural environment – in the hands of the end user. Specifically, we develop a logger application for Android G1 mobile phones and release the logger into the wild to collect traces of real user activity. We then show how the traces can be used to characterize power consumption, and guide the development of power optimizations.

In this paper we define and evaluate a framework for estimating the energy consumption of Java-based software systems. Our primary objective in devising the framework is to enable an engineer to make informed decisions when adapting a system’s architecture, such that the energy consumption on hardware devices with a finite battery life is reduced, and the lifetime of the system’s key software services increases. Our framework explicitly takes a componentbased perspective, which renders it well suited for a large class of today’s distributed, dynamic, and mobile applications. The framework allows the engineer to estimate the software system’s energy consumption at construction time and refine it at runtime. In a large number of distributed application scenarios, the framework showed very good precision on the whole, giving results that were within 5 % (and often less) of the actually measured power losses incurred by executing the software. While our empirical evidence suggests that the framework is broadly applicable as-is, our work to date has highlighted a number of future enhancements. 1.

We present an adaptive, feedback-based, energy estimation model for battery-powered embedded devices such as sensor network gateways and hand-held computers. Our technique maps hardware and software counters to energy consumption values using a set of first order, linear regression equations. Our system is novel in that it combines online and offline techniques to enable runtime power prediction. Our system employs an offline instantiated model that it continuously updates using feedback from a readily available battery monitor within the device. We empirically evaluate our model and detail its robustness, accuracy, and computational cost. We also analyze the stability of the model in the presence of feedback errors. We demonstrate that our approach can achieve an error rate of 1 % (extant techniques: 2.6 % to 4%) for computationally bound tasks and 6.6 % (extant techniques: 11%) for communication bound tasks.

In recent years, more and more transistors have been integrated within the GPU, which has resulted in steadily rising power consumption requirements. In this paper we present a preliminary scheme to statistically analyze and model the power consumption of a mainstream GPU (NVidia GeForce 8800gt) by exploiting the innate coupling among power consumption characteristics, runtime performance, and dynamic workloads. Based on the recorded runtime GPU workload signals, our trained statistical model is capable of robustly and accurately predicting power consumption of the target GPU. To the best of our knowledge, this study is the first work that applies statistical analysis to model the power consumption of a mainstream GPU, and its results provide useful insights for future endeavors of building energy-efficient GPU computing paradigms. 1.

Overprovisioning Circuit Capacity and Boosting Throughput. (Under the direction of As-

Abstract—Power modeling based on performance monitoring counters (PMCs) has attracted the interest of many researchers since it become a quick approach to understand and analyse power behavior on real systems. Moreover, several power aware policies use power models to guide their decisions and to trigger low-level mechanisms-e.g. manage processor frequency-. Hence, the information, the accuracy and the capacity for detecting power phases that a model provides is critical to increase the power-aware research chances and to improve the success of power savings techniques based on such models. In addition, the design of current processors have varied considerably with the inclusion of multiple cores with some resources shared on a single die. As a result, PMC-based power models warrant further investigation on current energy-efficient multicore processors. In this paper, we present a methodology to produce decomposable PMC-based power models on current multicore architectures. Besides from being able to estimate accurately the power consumption, the models provide per component power consumption, supplying extra information about power behavior. Moreover, we analyse and validate their responsiveness –the capacity to detect power phases–. We produce a set of power models for an Intel R○ Core TM 2 Duo, modeling one or two cores for a wide set of DVFS configurations. The models are empirically validated using the SPECcpu2006 and compared to other models built using existing approaches. Overall, we demonstrate that the proposed methodology produces more accurate and responsive power models, showing error ranges between [1.89-6] % and almost 100 % accuracy in detecting phase variations above 0.5 watts. I.

The Dissertation Committee for Shiwen Hu Certifies that this is the approved version of the following dissertation:

Abstract — This paper proposes an energy characterization framework which helps designers in developing a fast and accurate energy model for a target processor-based system. We use a linear model for energy estimation and we find the coefficients of the model using Linear Programming (LP). We use our approach for estimating the energy consumption of two commercial microprocessors with their on-chip caches and an offchip SDRAM. Experimental results demonstrate that the error of our technique is on an average 3 % and worst case 16 % compared to the gate-level estimation results. Once the model has been developed, the energy consumption of an application program can be estimated with the speed of 300,000 instructions per second. I.