Abstract. In recent years more and more security sensitive applications use passive smart devices such as contactless smart cards and RFID tags. Cost constraints imply a small hardware footprint of all components of a smart device. One particular problem of all passive smart devices such as RFID tags and contactless smart cards are the harsh power constraints. On the other hand, active smart devices have to minimize energy consumption. Recently, many lightweight block ciphers have been published. In this paper we present three different architecture of the ultra-lightweight algorithm present and highlight their suitability for both active and passive smart devices. Our implementation results of the serialized architecture require only 1000 GE. To the best of our knowledge this is the smallest hardware implementation of a cryptographic algorithm with a moderate security level. 1

Abstract. SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards or processors. In this paper, we investigate its hardware performances in a 0.13 µm CMOS technology. For these purposes, different designs are detailed. First, a single clock cycle per round loop architecture is implemented. Beyond its low cost performances, a significant advantage of the proposed encryption core is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding. Second, a more realistic design with a reduced datapath combined with a serial communication interface is described in order to put forward the low-power opportunities of SEA. Finally, a minimum datapath is presented and its applicability to RFID encryption is discussed. Additionally to these results, performance comparisons with the AES Rijndael are proposed. They illustrate the interest of platform/context-oriented block cipher design and, as far as SEA is concerned, its low area requirements and reasonable efficiency. 1

Abstract. Wireless Sensor Networks (WSN) are seen as attractive solutions for various monitoring and controlling applications, a large part of which require cryptographic protection. Due to the strict cost and power consumption requirements, their cryptographic implementations should be compact and energy-efficient. In this paper, we survey hardware architectures proposed for Advanced Encryption Standard (AES) implementations in low-cost and low-power devices. The survey considers both dedicated hardware and specialized processor designs. According to our review, currently 8-bit dedicated hardware designs seem to be the most feasible solutions for embedded, low-power WSN nodes. Alternatively, compact special functional units can be used for extending the instruction sets of WSN node processors for efficient AES execution. 1

Abstract. Actual and future developments of the automotive market (e.g. the AUTOSAR project or car2car communication systems) will increase the need for a suitable cryptographic infrastructure in modern vehicles. A core component for such a generic cryptographic core is a secure cryptographic hash function, because these functions are the base for a lot of applications like challenge-reponse authentication systems and digital signature schemes. In the present paper we evaluate the SHA-3 candidate Grøstl with respect to area requirements, which play a very important role for cost-sensitive markets. The National Institute of Standards and Technology (NIST) has started a competition for a new secure hash standard. In this context third party implementations of all proposed hash functions are regarded as an important part of the competition. We chose to implement the Grøstl hash function for FPGAs, for its resemblance to AES. More precisely we developed two optimized versions, one optimized for throughput, the other one for area. Both implementations improve the results and estimates presented in the original submission to the competition. The performance of both implementations may be improved further, thus Grøstl seems to be a good candidate for implementations on medium sized FPGAs. Besides that, it is shown that Grøstl needs a significant amount of resources, which will hinder its use for automotive applications.

Abstract—This paper proposes a low-cost reconfigurable architecture for AES algorithm. The proposed architecture separates SubBytes and MixColumns into two parallel data path, and supports different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The throughput and power consumption can be adjusted by changing the number of S-box running in this design. Using the TSMC 0.18µm CMOS standard cell library, a very low-cost implementation of 7K Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the minimum throughput is 114Mbps while only using 1 S-Box. Keywords—AES, Reconfigurable architecture, low cost. A