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12
Synthesis of speed independent circuits based on decomposition
 In ASYNC 2004
, 2004
"... This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the STG to include only transitions on the output of interest and ..."
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This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the STG to include only transitions on the output of interest and its trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals which must be reintroduced into the STG to obtain CSC. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full state space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool nutas (NiiUtah Timed Asynchronous circuit Synthesis system), and its very first version is available at
On Timing Analysis of Combinational Circuits
 In FORMATS’03, LNCS 2791
, 2003
"... Abstract. In this paper we report some progress in applying timed automata technology to largescale problems. We focus on the problem of finding maximal stabilization time for combinational circuits whose inputs change only once and hence they can be modeled using acyclic timed automata. We develop ..."
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Abstract. In this paper we report some progress in applying timed automata technology to largescale problems. We focus on the problem of finding maximal stabilization time for combinational circuits whose inputs change only once and hence they can be modeled using acyclic timed automata. We develop a “divideandconquer” methodology based on decomposing the circuit into subcircuits and using timed automata analysis tools to build conservative lowcomplexity approximations of the subcircuits to be used as inputs for the rest of the system. Some preliminary results of this methodology are reported. 1
Verification of timed circuits with failure directed abstractions
 In 21st International Conference on Computer Design (ICCD
, 2003
"... Abstract — This paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not ..."
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Abstract — This paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not occur. To each subproblem, abstraction is applied using safe transformations to reduce the complexity of verification. The abstraction preserves all essential behaviors conservatively for the specific failure model in the concrete description. Therefore, no violations of the given failure model are missed when only the abstract description is error trace to either find a concrete error trace or report that it is a false negative. This paper presents results using the proposed failure directed abstractions as applied to several large timed circuit designs. Index Terms — timed circuits, formal verification, abstraction. I.
Automatic abstraction for verification of cyberphysical systems
 In Proc. of ICCPS
, 2010
"... Models of cyberphysical systems are inherently complex since they must represent hardware, software, and the physical environment. Formal verification of these models is often precluded by state explosion. Fortunately, many important properties may only depend upon a relatively small portion of th ..."
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Cited by 5 (1 self)
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Models of cyberphysical systems are inherently complex since they must represent hardware, software, and the physical environment. Formal verification of these models is often precluded by state explosion. Fortunately, many important properties may only depend upon a relatively small portion of the system being accurately modeled. This paper presents an automatic abstraction methodology that simplifies the model accordingly. Preliminary results on a faulttolerant temperature sensor are encouraging.
Efficient verification of hazardfreedom in gatelevel timed asynchronous circuits
 IEEE Transactions on CAD, page
"... This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit timing information for optimization throughout the entire design process. In asynchronous circuits, correct operation require ..."
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This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit timing information for optimization throughout the entire design process. In asynchronous circuits, correct operation requires that there are no hazards in the circuit implementation. Therefore, when designing an asynchronous circuit, each internal node and output of the circuit must be verified for hazardfreedom to ensure correct operation. Current verification algorithms for timed asynchronous circuits require an explicit state exploration often resulting in state explosion for even modest sized examples. The goal of this work is to abstract the behavior of internal nodes and utilize this information to make a conservative determination of hazardfreedom for each node in the circuit. Experimental results indicate that this approach is substantially more efficient than existing timing verification tools. These results also indicate that this method scales well for large examples. It is capable of analyzing circuits in less than a second that could not be previously analyzed. While this method is conservative in that some false hazards may be reported, our results indicate that the number of false hazards is small. 1.
Synthesis of Timed Circuits Based on Decomposition
"... Abstract—This paper presents a decompositionbased method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed signal transition graph (STG) to include only transi ..."
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Abstract—This paper presents a decompositionbased method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed signal transition graph (STG) to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals, which must be reintroduced into the STG to obtain complete state coding. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which fullstatespace methods cannot be successfully applied. The proposed method has been implemented as a part of our tool NiiUtah Timed Asynchronous circuit Synthesis system (nutas), and its first version is available at
Verifying Synchronization Strategies
"... Abstract. Over the years, there have been numerous methods proposed to solve the synchronization problem. Many of these methods, however, are not sufficiently evaluated before being utilized leading to problems in a system design that are difficult to diagnose and solve. Therefore, it is crucial tha ..."
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Abstract. Over the years, there have been numerous methods proposed to solve the synchronization problem. Many of these methods, however, are not sufficiently evaluated before being utilized leading to problems in a system design that are difficult to diagnose and solve. Therefore, it is crucial that strategies for synchronization are critically analyzed and verified before being incorporated in a system design. This paper reviews a number of the known methods for synchronization, discusses issues in their design, and presents techniques for their verification. 1 The Synchronization Problem While there have been many promising asynchronous design examples [48,4, 17,42,1], asynchronous design is still not seeing widespread use. One important reason for this is that asynchronous designs must communicate with other parts of the system which typically operate synchronously. Unfortunately, this is difficult to do reliably without substantial latency penalties. When this latency penalty is taken into account, most, if not all, of the performance advantage gained by an asynchronous design is lost. Even if no asynchronous modules are used, synchronous modules operating at different clock rates or out of phase can have the same problem. The latter problem is becoming more significant as it becomes increasingly difficult to distribute a single global clock to all parts of the chip. Many designers today are considering the necessity of having multiple
ABSTRACT On Timed Components and their Abstraction
"... We develop a new technique for generating smallcomplexity abstractions of timed automata that provide an approximation of their timed inputoutput behavior. This abstraction is obtained by first augmenting the automaton with additional input clocks, computing the “reachable ” timed automaton that c ..."
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We develop a new technique for generating smallcomplexity abstractions of timed automata that provide an approximation of their timed inputoutput behavior. This abstraction is obtained by first augmenting the automaton with additional input clocks, computing the “reachable ” timed automaton that corresponds to the augmented model and finally “hiding ” the internal variables and clocks of the system. As a result we obtain a timed automaton that does not allow any qualitative behavior which is infeasible due to timing constraints, and which maintains a relaxed form of the timing constraints associated with the feasible behaviors. We have implemented this technique and applied it to several examples from different application domains.
A compositional Minimization Approach for Large Asynchronous Design Verification
"... Abstract. This paper presents a compositional minimization approach with efficient state space reductions for verifying nontrivial asynchronous designs. These reductions can result in a reduced model that contains the exact same set of observably equivalent behavior in the original model, therefore ..."
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Abstract. This paper presents a compositional minimization approach with efficient state space reductions for verifying nontrivial asynchronous designs. These reductions can result in a reduced model that contains the exact same set of observably equivalent behavior in the original model, therefore no false counterexamples are produced at the end of verification on the reduced model. This approach allows designs that cannot be handled monolithically or with partialorder reduction to be verified without difficulty. The experimental results show significant scaleup of the compositional minimization approach using these reductions on a number of large asynchronous designs.
1 Efficient Verification of HazardFreedom in GateLevel Timed Asynchronous Circuits
"... Abstract — This article presents an efficient method for verifying hazard freedom in gatelevel timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that are optimized using explicit timing information. In asynchronous circuits, correct operation requires that there are n ..."
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Abstract — This article presents an efficient method for verifying hazard freedom in gatelevel timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that are optimized using explicit timing information. In asynchronous circuits, correct operation requires that there are no hazards in the circuit implementation. Therefore, when designing an asynchronous circuit, each internal node and output of the circuit must be verified for hazardfreedom to ensure correct operation. Current verification algorithms for timed circuits require an explicit state exploration often resulting in state explosion for even modest sized examples. The goal of this work is to abstract the behavior of internal nodes and utilize this information to make a conservative determination of hazardfreedom for each node in the circuit. Experimental results indicate that this approach is substantially more efficient than existing timing verification tools. These results also indicate that this method scales well for large examples in that it is capable of analyzing circuits in less than a second that could not be previously analyzed. While this method is conservative in that some false hazards may be reported, our results indicate that their number is small. Index Terms — Verification, hazardfreedom, timed asynchronous circuits, technology mapping