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...systems. For example, it can be extended by the routing supply and demand system in order to optimize routability during placement [30], or D can be used to optimize the temperature profile of a chip =-=[31]-=-. B. Hold Force To spread the modules iteratively over the chip, the move force is used. However, besides the move force, the net force is acting on the modules and minimizes the netlength. Thus, the ...

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...al net-switching power and 11.4% reduction in total power, with 2.0% timing, 1.2% cell area and 11.5% runtime degradation. The organization of this paper is as follows. Section 2 summarizes known approaches to net switching power minimization. Sections 3 and 4 describe the techniques of activitybased register clustering and activity-based net weighting. Experimental results are reported in Section 5 using a complete industrial flow. The paper concludes in Section 6. 2. PREVIOUS WORK Assigning net weights according to switching activities is commonly applied to reduce total net switching power [3, 14, 17, 19, 21]. For example, in a recent paper on temperatureaware placement [14], net weights are assigned proportional to the product of switching rate and pin count, in order to reduce net switching power. Traditional clock-tree construction methods [4, 10, 11] focus on minimizing clock-tree wirelength or clock skew. On the other hand, more recent studies [6, 13, 8, 18] agree that clock trees are the largest consumers of power in microprocessors, and a number of techniques have been proposed to reduce clock-tree power including clock gating [2, 6, 7, 15], buffer sizing [1, 20], and multiple-supply voltag...

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... charge density D. This charge density creates a potential Φ, which can be solved by the Poisson equation: (6) △Φ=−D (7) The Poisson equation can be solved efficiently by a geometric multigrid solver =-=[27]-=-, [20]. If chip’s charge density DChip is constant then module density d is exactly charge density D plus DChip [12]. Therefore, no difference between module density d and charge density D is made fur...

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...e authors observe that an effective way to allocate decaps is to distribute them to all grid nodes, assigning more decaps to grid nodes of the blocks with high switching rates. Some previous works [4]=-=[13]-=- propose to reduce power noise by spreading the frequently switching cells evenly across the chip to eliminate hot spots. In [4], the authors include thermal cost function in a partition-based placer....

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...on 7, see [7]. Minimizing power consumption can be achieved by controlling the weight of these nets, which are most responsible for the power consumption (e.g. nets with a high switching rate). See =-=[6]-=- for further details. Sophisticated extensions to the proposed method have been developed to meet timing requirements more precisely, e.g. switching to a Steiner-tree model during timingdriven place...

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... on the thermal placement problem can be categorized into four classes on the basis of algorithms used: • Simulated annealing approach [4]; • Approximation algorithms [5]; • Force-directed algorithms =-=[6]-=-; • Partition-based algorithms [7]. In [4], the authors propose a simulated annealing approach, even though this approach can handle most of the necessary properties, it suffers from long run time whe...