rently being developed to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consump-tion. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools, the 3D Floorplan and Power/Ground (P/G) Co-synthesis tool is developed in this work, which develops the floorplan and the P/G network concurrently. Most current 3D IC floorplanners neglect the effects of the 3D P/G network on the design, which may lead to large IR drops in the circuit. To create feasible floorplans with efficient P/G networks, the 3D Floorplan and P/G Co-synthesis tool optimizes the floorplan in terms of wirelength, area and P/G routing area and IR drops. The tool integrates a 3D B*-tree floorplan representation, a resistive P/G mesh, and a Simulated Annealing (SA) engine to explore the 3D floorplan and P/G network. The results of experiments using the 3D Floorplan and P/G Co-synthesis tool show that 3D ICs tend to increase the P/G routing area while decreasing the IR drops in the circuit. By considering the IR drop while floorplanning, exploring the 3D P/G design space, and

Abstract–Due to the high integration on vertical stacked layers, power/ground network design becomes one of the critical challenges in 3D IC design. With the leakage-thermal dependency, the increasing on-chip temperature in 3D designs has serious impact on IR drop due to the increased wire resistance and increased leakage current. Power/ground (P/G) TSVs can help to relieve the IR drop violation by vertically connecting the on-chip P/G networks on different layers. However, most previous work only fulfills a margin of the full potential of PG TSVs planning since the P/G grids are restricted in a uniform topology. Besides, the overlook of resistance variation and leakage current will make the results less accurate. In this paper, we present an efficient thermal-aware P/G TSVs planning algorithm based on a sensitivity model with temperature-dependent leakage current considered. The proposed method can overcome the limitation of uniform P/G grid topology and make full use of P/G TSVs planning for the optimization of P/G network by allowing short wires to connect the P/G TSVs to P/G grids in non-uniform topology. Moreover, with resistance variation and increased leakage current caused by high temperature in 3D ICs, more accurate result can be obtained. Both the theoretical analysis and experimental results show the efficiency of our approach. Results show that neglecting thermal impacts on power delivery can underestimate IR drop by about 11%. To relieve the severe IR drop violation, 51.8 % more P/G TSVs are needed than the cases without thermal impacts considered. Results also show that our P/G TSV planning based on the sensitivity model can reduce max IR drop by 42.3 % and reduce the number of violated nodes by 82.4%. I.

Abstract — In this paper we demonstrate the methodology for designing and optimizing the LEON3 multi-core microprocessor in 3D stacked ICs. Based on GDSII-level details, we compare the 3D IC implementations as well as the traditional 2D IC implementation. For 3D IC implementation, we compare three partitioning styles: core-level, block-level, and gate-level. These partitioning styles represent three most relevant 3D implementa-tion choices. The design methodology for such partitioning styles and their implications on the physical layout are discussed. Then we propose two methods to perform timing optimizations for 3D stacked ICs: timing scaling and timing budgeting. By analyzing the timing constraints from each method and the effects on the timing results and the layout, we show that each method has different impacts on the overall design quality. Lastly, we discuss additional 3D optimization opportunities. I.

In this article, we propose a design methodology using two complementary techniques to address high-frequency inductive noise in the early design phase of a microprocessor. First, we propose a noise-aware floorplanning technique that uses microarchitectural profile information to create noise-aware floorplans. Second, we present the design of a dynamic inductive-noise controlling mechanism at the microarchitectural level, which limits the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchi-tectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt alleviation technique is the first that takes the processor’s floorplan, as well as its power-pin distribution, into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability by up to 7 times, with an average performance overhead of 4.0%. In addition, our floorplan reduces the noise margin violations using our noise-aware floorplan by an average of 56.3 % while reducing the decap budget by 28%.

Abstract—In this paper, we present the first optical router for 3-D system-on-package (SOP). Recent advances in optical device integration for SOP offer drastic advantages over electrical inter-connects. We propose efficient algorithms for the construction of timing and congestion-driven waveguides taking into account the optical resource constraints. Our experimental results suggest that smart placement of waveguides coupled with other routing tech-niques can reduce electrical wirelength by 11 % and improve per-formance by 23%, when a single optical layer is introduced for every placement layer. Index Terms—Optical routing, system-on-package (SOP), wave-guide construction. I.

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In recent years, scaling down device dimension or utilizing novel crystallization technologies provide the opportunity of applying much more devices to integrated circuit fabrication. Due to emerging DSM effects, the research about routing has drawn much attention in VLSI Physical Design. In this paper, we will focus on three issues. One, the traditional Manhattan routing has longer length and larger delay than X-Architecture routing. Second, in multilayer routing, the delay of one via is much larger than the delay of Manhattan routing. Third, since a routed segment and macro cell should be considered as obstacles, we must consider the rectangle and non-rectangle obstacles, and consider the number of vias as well. Our algorithm can handle both rectangle obstacles and non-rectangle obstacles, and we use fewer vias and X-Architecture router by region to construct the multilayer routing trees. The main purpose is to obtain an obstacles-avoiding routing tree of minimal wire length and minimal delay.

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Billions of transistors are placed in one single chip (SoC) with advanced manufacturing technology. Further development is obstructed by the ability to the manufacture of SoC and the signal integrity. Stacking IC is an alternative choice when we design a highperformance high-density chip. Design flow (especially physical design) is facing different issues when compared with 2D IC design. The location of the I/Os seriously affect the number of 3D-Vias and their total area in the stacking IC. This paper proposes a Stacking IC architecture and the corresponding design flow to solve the I/O and 3D-Via problems. In this flow, we have developed a system partition approach to minimize the number of 3D-Vias and balance the I/O number of each tier, and modified one traditional floorplan method to optimize the I/O and module locations. The experimental results are encouraging in the GSRC benchmarks. Compared with greedy and intuitive methods, our framework reduces the number of 3D-Vias by 30.02 % on the average and can balance the I/O count of each tier. The dead space of the final floorplan is reduced by 14.13%.