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1 HighLevel Interconnect Model for the Quantum Logic Array Architecture
, 2008
"... We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportationbased logical interconnect. The design goal of the the quantum logic array architecture is to ..."
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We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportationbased logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a largescale quantum architecture that solves the primary challenges of systemlevel reliability and data distribution over large distances. The QLA’s logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048bit number using Shor’s quantum factoring algorithm. Our physicallevel assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.
RANDOM ROUTING AND CONCENTRATION IN QUANTUM SWITCHING NETWORKS
, 2008
"... Flexible distribution of data in the form of quantum bits or qubits among spatially separated entities is an essential component of envisioned scalable quantum computing architectures. Accordingly, we consider the problem of dynamically permuting groups of quantum bits, i.e., qubit packets, using n ..."
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Flexible distribution of data in the form of quantum bits or qubits among spatially separated entities is an essential component of envisioned scalable quantum computing architectures. Accordingly, we consider the problem of dynamically permuting groups of quantum bits, i.e., qubit packets, using networks of reconfigurable quantum switches. We demonstrate and then explore the equivalence between the quantum process of creation of packet superpositions and the process of randomly routing packets in the corresponding classical network. In particular, we consider an n × n Baseline network for which we explicitly relate the pairwise inputoutput routing probabilities in the classical random routing scenario to the probability amplitudes of the individual packet patterns superposed in the quantum output state. We then analyze the effect of using quantum random routing on a classically nonblocking configuration like the Beneš network. We prove that for an n × n quantum Beneš network, any input packet assignment with no output contention is probabilistically selfroutable. In particular, we prove that with random routing
Microcoded Architectures for IonTrap Quantum Computers
"... In this paper we present the first ever systematic design space exploration of microcoded software fault tolerant iontrap quantum computers. This exploration reveals the critical importance of a welltuned microcode for providing high performance and ensuring system reliability. In addition, we find ..."
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In this paper we present the first ever systematic design space exploration of microcoded software fault tolerant iontrap quantum computers. This exploration reveals the critical importance of a welltuned microcode for providing high performance and ensuring system reliability. In addition, we find that, despite recent advances in the reliability of quantum memory, the impact of errors due to stored quantum data is now, and will continue to be, a major source of systemic error. Finally, our exploration reveals a single design which out performs all others we considered in run time, fidelity and area. For completeness our design space exploration includes designs from prior work [13] and we find a novel design that is 1 2 the size, 3 times as fast, and an order of magnitude more reliable. 1. Introduction & Prior
Design of a Universal Logic Block for FaultTolerant Realization of any Logic Operation in TrappedIon Quantum Circuits
"... Abstract This paper presents a physical mapping tool for quantum circuits, which generates the optimal Universal Logic Block (ULB) that can, on average, perform any logical faulttolerant (FT) quantum operations with the minimum latency. The operation scheduling, placement, and qubit routing proble ..."
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Abstract This paper presents a physical mapping tool for quantum circuits, which generates the optimal Universal Logic Block (ULB) that can, on average, perform any logical faulttolerant (FT) quantum operations with the minimum latency. The operation scheduling, placement, and qubit routing problems tackled by the quantum physical mapper are highly dependent on one another. More precisely, the scheduling solution affects the quality of the achievable placement solution due to resource pressures that may be created as a result of operation scheduling whereas the operation placement and qubit routing solutions influence the scheduling solution due to resulting distances between predecessor and current operations, which in turn determines routing latencies. The proposed flow for the quantum physical mapper captures these dependencies by applying (i) a loose scheduling step, which transforms an initial quantum data flow graph into one that explicitly captures the nocloning theorem of the quantum computing and then performs instruction scheduling based on a modified forcedirected scheduling approach to minimize the resource contention and quantum circuit latency, (ii) a placement step, which uses timingdriven instruction placement to minimize the approximate routing latencies while making iterative calls to the aforesaid forcedirected scheduler to correct scheduling levels of quantum operations as needed, and (iii) a routing step that finds dynamic values of routing latencies for the qubits. In addition to the quantum physical mapper, an approach is presented to determine the single best ULB size for a target quantum circuit by examining the latency of different
State of the Art in Quantum Computer Architectures
, 2011
"... Quantum computer architecture as a field remains in its infancy, but carries much promise for producing machines that vastly exceed current classical capabilities, for certain systems designed to solve certain problems. It must be recognized that large systems are not simply larger versions of smal ..."
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Quantum computer architecture as a field remains in its infancy, but carries much promise for producing machines that vastly exceed current classical capabilities, for certain systems designed to solve certain problems. It must be recognized that large systems are not simply larger versions of small systems. These notes review the fronts on which progress must be made for such systems to be realized: experimental development of quantum computing technologies, and theoretical work in quantum error correction, quantum algorithms, and computer architecture. Key open problems are discussed from both a technical and organizational point of view, and specific recommendations for increasing the vibrancy of the architecture effort are given.
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
"... The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, “seaofqubits ” architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system ..."
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The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, “seaofqubits ” architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems. 1
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
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Practical Fault Tolerance for Quantum Circuits
"... personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires pri ..."
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personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific
Designing a MillionQubit Quantum Computer Using a Resource Performance Simulator
"... The optimal design of a faulttolerant quantum computer involves finding an appropriate balance between the burden of largescale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be evaluated by quantitatively modeling the execution ..."
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The optimal design of a faulttolerant quantum computer involves finding an appropriate balance between the burden of largescale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be evaluated by quantitatively modeling the execution of quantum logic operations on a realistic quantum hardware containing limited computational resources. In this work, we report a complete performance simulation software tool capable of (1) searching the hardware design space by varying resource architecture and technology parameters, (2) synthesizing and scheduling a faulttolerant quantum algorithm within the hardware constraints, (3) quantifying the performance metrics such as the execution time and the failure probability of the algorithm, and (4) analyzing the breakdown of these metrics to highlight the performance bottlenecks and visualizing resource utilization to evaluate the adequacy of the chosen design. Using this tool, we investigate a vast design space for implementing key building blocks of Shor’s algorithm to factor a 1,024bit number with a baseline budget of 1.5 million qubits. We show that a trappedion quantum computer designed with twice as many qubits and onetenth of the baseline infidelity of the communication channel can factor a 2,048bit integer in less than 5 months. CCS Concepts: Computer systems organization→Quantum computing; Hardware→ Quantum error correction and fault tolerance