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240
Monotone Complexity
, 1990
"... We give a general complexity classification scheme for monotone computation, including monotone spacebounded and Turing machine models not previously considered. We propose monotone complexity classes including mAC i , mNC i , mLOGCFL, mBWBP , mL, mNL, mP , mBPP and mNP . We define a simple ..."
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Cited by 2837 (11 self)
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We give a general complexity classification scheme for monotone computation, including monotone spacebounded and Turing machine models not previously considered. We propose monotone complexity classes including mAC i , mNC i , mLOGCFL, mBWBP , mL, mNL, mP , mBPP and mNP . We define a simple notion of monotone reducibility and exhibit complete problems. This provides a framework for stating existing results and asking new questions. We show that mNL (monotone nondeterministic logspace) is not closed under complementation, in contrast to Immerman's and Szelepcs 'enyi's nonmonotone result [Imm88, Sze87] that NL = coNL; this is a simple extension of the monotone circuit depth lower bound of Karchmer and Wigderson [KW90] for stconnectivity. We also consider mBWBP (monotone bounded width branching programs) and study the question of whether mBWBP is properly contained in mNC 1 , motivated by Barrington's result [Bar89] that BWBP = NC 1 . Although we cannot answer t...
Parallel merge sort
 SIAM Journal of Computing
, 1988
"... Abstract. We give a parallel implementation of merge sort on a CREW PRAM that uses n processors and O(logn) time; the constant in the running time is small. We also give a more complex version of the algorithm for the EREW PRAM; it also uses n processors and O(logn) time. The constant in the runnin ..."
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Cited by 316 (3 self)
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Abstract. We give a parallel implementation of merge sort on a CREW PRAM that uses n processors and O(logn) time; the constant in the running time is small. We also give a more complex version of the algorithm for the EREW PRAM; it also uses n processors and O(logn) time. The constant in the running time is still moderate, though not as small. 1.
Information Theory and Communication Networks: An Unconsummated Union
 IEEE Trans. Inform. Theory
, 1998
"... Information theory has not yet had a direct impact on networking, although there are similarities in concepts and methodologies that have consistently attracted the attention of researchers from both fields. In this paper, we review several topics that are related to communication networks and that ..."
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Cited by 183 (7 self)
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Information theory has not yet had a direct impact on networking, although there are similarities in concepts and methodologies that have consistently attracted the attention of researchers from both fields. In this paper, we review several topics that are related to communication networks and that have an information theoretic flavor, including multiaccess protocols, timing channels, effective bandwidth of bursty data sources, deterministic constraints on datastreams, queueing theory, and switching networks. Keywords Communication networks, multiaccess, effective bandwidth, switching I. INTRODUCTION Information theory is the conscience of the theory of communication; it has defined the "playing field" within which communication systems can be studied and understood. It has provided the spawning grounds for the fields of coding, compression, encryption, detection, and modulation and it has enabled the design and evaluation of systems whose performance is pushing the limits of wha...
Private Circuits: Securing Hardware against Probing Attacks
 In Proceedings of CRYPTO 2003
, 2003
"... Abstract. Can you guarantee secrecy even if an adversary can eavesdrop on your brain? We consider the problem of protecting privacy in circuits, when faced with an adversary that can access a bounded number of wires in the circuit. This question is motivated by side channel attacks, which allow an a ..."
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Cited by 130 (7 self)
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Abstract. Can you guarantee secrecy even if an adversary can eavesdrop on your brain? We consider the problem of protecting privacy in circuits, when faced with an adversary that can access a bounded number of wires in the circuit. This question is motivated by side channel attacks, which allow an adversary to gain partial access to the inner workings of hardware. Recent work has shown that side channel attacks pose a serious threat to cryptosystems implemented in embedded devices. In this paper, we develop theoretical foundations for security against side channels. In particular, we propose several efficient techniques for building private circuits resisting this type of attacks. We initiate a systematic study of the complexity of such private circuits, and in contrast to most prior work in this area provide a formal threat model and give proofs of security for our constructions.
Slowing down sorting networks to obtain faster sorting algorithms
 Journal of the ACM
, 1987
"... Abstract. Megiddo introduced a technique for using a parallel algorithm for one problem to construct an efftcient serial algorithm for a second problem. This paper provides a general method that trims a factor of O(log n) time (or more) for many applications of this technique. ..."
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Cited by 112 (0 self)
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Abstract. Megiddo introduced a technique for using a parallel algorithm for one problem to construct an efftcient serial algorithm for a second problem. This paper provides a general method that trims a factor of O(log n) time (or more) for many applications of this technique.
merging, and sorting in parallel models of computation
 in “Proc. 14th Annual ACM Sympos. on Theory of Cornput
, 1982
"... A variety of models have been proposed for the study of synchronous parallel computation. These models are reviewed and some prototype problems are studied further. Two classes of models are recognized, fixed connection networks and models based on a shared memory. Routing and sorting are prototype ..."
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Cited by 110 (3 self)
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A variety of models have been proposed for the study of synchronous parallel computation. These models are reviewed and some prototype problems are studied further. Two classes of models are recognized, fixed connection networks and models based on a shared memory. Routing and sorting are prototype problems for the networks; in particular, they provide the basis for simulating the more powerful shared memory models. It is shown that a simple but important class of deterministic strategies (oblivious routing) is necessarily inefficient with respect to worst case analysis. Routing can be viewed as a special case of sorting, and the existence of an O(log n) sorting algorithm for some n processor fixed connection network has only recently been established by Ajtai, Komlos, and Szemeredi (“15th ACM Sympos. on Theory of Cornput., ” Boston, Mass., 1983, pp. l9). If the more powerful class of shared memory models is considered then it is possible to simply achieve an O(log n loglog n) sort via Valiant’s parallel merging algorithm, which it is shown can be implemented on certain models. Within a spectrum of shared memory models, it is shown that loglogn is asymptotically optimal for n processors to merge two sorted lists containing n elements. 0 1985 Academic Press, Inc.
An efficient parallel biconnectivity algorithm
 SIAM J. Computing
, 1985
"... Abstract. In this paper we propose a new algorithm for finding the blocks (biconnected components) of an undirected graph. A serial implementation runs in O(n + m) time and space on a graph of n vertices and m edges. A parallel implementation runs in O(log n) time and O(n + m) space using O(n + m) p ..."
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Cited by 107 (5 self)
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Abstract. In this paper we propose a new algorithm for finding the blocks (biconnected components) of an undirected graph. A serial implementation runs in O(n + m) time and space on a graph of n vertices and m edges. A parallel implementation runs in O(log n) time and O(n + m) space using O(n + m) processors on a concurrentread, concurrentwrite parallel RAM. An alternative implementation runs in O(n2/p) time and O(n2) space using any number p < = n/log n of processors, on a concurrentread, exclusivewrite parallel RAM. The last algorithm has optimal speedup, assuming an adjacency matrix representation of the input. A general algorithmic technique that simplifies and improves computation of various functions on trees is introduced. This technique typically requires O(log n) time using processors and O(n) space on an exclusiveread exclusivewrite parallel RAM.