The advent of new families of reconfigurable integrated circuits makes it possible for artificial evolution to manipulate a real physical substrate to produce electronic circuits evaluated in the real world. This raises new issues about the potential nature of electronic circuits, because evolution uses no modelling, abstraction or analysis; only physical behaviour. The simplifying constraints of conventional design methodologies can be dropped, allowing evolution to exploit the full range of physical dynamics available from the silicon medium. This claim is investigated theoretically and in simulation, before presenting the first reported direct evolution of the configuration of a Field Programmable Gate Array (FPGA). Evolution is seen to harness its natural dynamics and exploit them in achieving a real-world task. 1 Introduction There is a type of Very-Large Scale Integrated circuit (a VLSI chip) known as a Field-Programmable Gate Array (FPGA). These chips do not have a predetermin...

. Artificial evolution can operate upon reconfigurable electronic circuits to produce efficient and powerful control systems for autonomous mobile robots. Evolving physical hardware instead of control systems simulated in software results in more than just a raw speed increase: it is possible to exploit the physical properties of the implementation (such as the semiconductor physics of integrated circuits) to obtain control circuits of unprecedented power. The space of these evolvable circuits is far larger than the space of solutions in which a human designer works, because to make design tractable, a more abstract view than that of detailed physics must be adopted. To allow circuits to be designed at this abstract level, constraints are applied to the design that limit how the natural dynamical behaviour of the components is reflected in the overall behaviour of the system. This paper reasons that these constraints can be removed when using artificial evolution, releasing huge potent...

Artificial evolution as a design methodology for hardware frees many of the simplifying constraints normally imposed to make design by humans tractable. However, this freedom comes at some cost, and a whole fresh set of issues must be considered. Standard genetic algorithms are not generally appropriate for hardware evolution when the number of components need not be predetermined. The use of simulations is problematic, and robustness in the presence of noise or hardware faults is important. We present theoretical arguments, and illustrate with a physical piece of hardware evolved in the real-world (`intrinsically evolved' hardware). A simple asynchronous digital circuit controls a real robot, using a minimal sensorimotor control system of 32 bits of RAM and a few flip-flops to co-ordinate sonar pulses and motor pulses with no further processing. This circuit is tolerant to single-stuck-at faults in the RAM. The methodology is applicable to many types of hardware, including Field-Programmable Gate Arrays (FPGA's).

Test patterns for large VLSI systems are often determined from the knowledge of the circuit function. A fault simulator is then used to find the effectiveness of the test patterns in detecting gate-level “stuck-at” faults. Existing gate-level fault simulation techniques suffer prohibitively expensive performance penalties when applied to the modern VLSI systems of larger sizes. Also, post-synthesis findings of such test generation and fault simulation efforts are too late in the design cycle to be useful for Design-For-Test (DFT) related improvements in the architecture. Therefore, an effective Register-Transfer Level (RTL) fault model is highly desirable. In this thesis, a novel procedure that supports RTL fault simulation and generates an estimate of the gate-level fault coverage for a given set of test patterns is proposed. This procedure is based on new RTL fault model, fault-injection algorithm, application of stratified sampling theory, and stratum weight extraction techniques. The VLSI system consists of interconnections of modules described in an RTL language. The proposed RTL fault model and

To create a combinational ATPG model for an acyclic sequential circuit, all unbalanced fanouts, i.e., fanouts reconverging with different sequential depths, are moved toward primary inputs using a retiming-like transformation. All flipflops are then shorted and unbalanced primary input fanouts are split as additional primary inputs. A combinational test vector for a fault in this model is converted into a vector sequence that detects the corresponding fault in the original circuit. An analysis classifies the undetected faults in this model as either untestable or multiply-testable. The latter, typically less than 5 % of all faults, are modeled as special single faults in the combinational model. This procedure correctly treats various types of faults, namely, (a) faults detectable by repeating a pattern, (b) faults only detectable by non-repeated patterns, (c) faults only testable as multiple faults in the combinational model, and (d) sequentially untestable faults. IS-CAS ’89 benchmark results verify that the given procedure achieves identical fault coverage and efficiency as a sequential ATPG and uses less CPU time.

Producing modular products that combine modules with the consideration of product performance, e.g., testability of electronic systems, is frequently stated as a design goal. However, most of mechatronic frameworks (models) discussed in the literature do not consider testability of electronic subsystems of mechatronic products. This paper assumes that the product modules have been established, and aims at the development of modular mechatronic products with the consideration of testability of electronic subsystems as a performance criterion. The generation of modular products and module testability issues are discussed. Testability points, testability values, and access paths for a module/system are crucial to the generation of modular mechatronic products. A generalized label-correcting algorithm is developed to determine the points of focus, testability values, and access paths in modules. This paper contributes to the development of modular mechatronic products with the consideration of testability of electronic subsystems.

Abstract—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. We propose a low-overhead scan design methodology that employs a new test-point insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability and observability of the selected signals, the test points are used here to establish scan paths through the functional logic. The proposed technique reuses the functional logic for scan operations; as a result, the design-fortestability overhead on area or timing can be minimized. We show an algorithm that uses the new test-point insertion technique to reduce the area overhead for the full-scan design. We also discuss its application to the timing-driven partial-scan design. Index Terms—Design for testability. I.

All rights reserved, including the right to reproduce this report, or portions thereof, in any form. New digital designs often include scan chains; high quality economical test is the reason. A scan chain allows easy access to internal combinational logic by converting bistable elements, latches and flip-flops, into a shift register. Test patterns are scanned in, applied to the internal circuitry, and the results are scanned out for comparison. While many techniques exist for testing the combinational circuitry, little attention has been paid to testing the bistable elements themselves. The bistable elements are typically tested by shifting in a sequence of zeroes and ones. This test can miss many defects inside the bistable elements. A checking experiment is a sequence of inputs and outputs that contains enough information to extract the functionality of the circuit. A new approach, based on such sequences, can significantly reduce the number of defects missed. Simulation results show that as many as 20 percent of the faults in bistable elements can be missed by typical tests; essentially all of these missed faults are detected by checking experiments. Since the checking experiment is a functional test, it is

the final electronic copy of this thesis for form and content and recommend that it

Abstract—This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential benchmark circuits using HOPE—a fault simulator developed for synchronous sequential circuits that employs parallel fault simulation with heuristics to reduce simulation time in the context of designing space-efficient support hardware for built-in self-testing of very large-scale integrated circuits. The techniques realized in this paper take advantage of the basic ideas of sequence characterization previously developed and utilized by the authors for response data compaction in the case of ISCAS 85 combinational benchmark circuits, using simulation programs ATALANTA, FSIM, and COMPACTEST, under conditions of both stochastic independence and dependence of single and double line errors in the selection of specific gates for merger of a pair of output bit streams from a circuit under test (CUT). These concepts are then applied to designing efficient space compression networks in the case of full scan sequential benchmark circuits using the fault simulator HOPE. Index Terms—Built-in self-test (BIST), circuit under test (CUT), detectable error probability estimates, fault simulation using HOPE, Hamming distance, optimal sequence mergeability, response compaction, sequence weights, single stuck-line faults, space compactor. I.