Shape Analysis concerns the problem of determining "shape invariants"...

We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algorithm [HP96] for out-of-order instruction scheduling. Our approach is similar to the idea of uninterpreted function symbols [BD94]. We use symbolic values and instructions instead of concrete ones. This allows us to show the correctness of the machine independently of the actual instruction set architecture and the implementation of the functional units. Instead of using first order terms as in [BD94], we represent symbolic values with a new compact encoding. In addition, we apply some other reduction techniques to the model. This significantly reduces the state space and allows the use of highly efficient symbolic model checkers like SMV instead of special decision procedures. The correctness of the method has been proven formally with the PVS theorem prover. 1 Introduction Modern microprocessors are becoming ...

The verification of networks of processes by model-checking is discussed. Five classes of...

The symmetry reduction method is a technique designed to alleviate the combinatorial state space explosion problem by exploiting the symmetries of state spaces. This work describes a way how state space symmetries of a high-level Petri net formalism, algebraic system nets, can be detected and exploited during the reachability analysis. The main idea is that permuting the domains of data types used in nets produces corresponding permutations to the state space level. As the main