This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the distributed arithmetic of a finite impulse response (FIR) filter. Then, it shows a method to realize the WS function by an LUT cascade with k-input q-output cells. Furthermore, it 1) shows that LUT cascade realizations require much smaller memory than the single ROM realizations; 2) presents new design method for a WS function by arithmetic decomposition, and 3) shows design results of FIR filters using FPGAs with embedded memories.

In this paper, we introduce three types of multiplevalued content-addressable memories (CAMs): ordinary CAMs (CAMs), distance d CAMs, and *CAMs. Ordinary CAMs require an exact match, while *CAMs allow wildcard matches. In a distance d CAM, a match occurs even if at most d digits differ. Then, we define multiple-valued CAM functions represented by these CAMs. Next, we show an approach to realize each CAM function by an LUT cascade, which is a series connection of RAMs. Experimental results for both two-valued and multi-valued cases are shown.

Two types of programmable logic devices using LUTs (Look-Up Tables) are presented. An LUT cascade directly implements logic functions by a series connection of LUTs, while an emulator emulates an LUT cascade by sequentially accessing LUTs. The LUT cascade is faster, but has a limited logic capability, while the emulator is slower, but has a higher logic capability. LUT cascades and emulators can be directly generated from the BDDs of target functions. Their performances are easy to estimate. The C-measure that show the complexity of LUT cascades are also presented. Functions with small C-measures have efficient LUT cascade and emulator realizations. Classes of functions that are suitable for LUT cascade and emulator realizations are also presented. 1

First, this paper considers the number of LUTs to implement logic functions based on MUX-based realization and cascade realization. This is useful to quickly estimate the number of LUTs to implement the functions on a FPGA. Second, this paper shows an algorithm to realize logic functions by 6-LUTs using cascade and MUX-based realizations. It often produces smaller circuits than previous methods when the number of the input variables is smaller than 16. 1