Reconfigurable circuits and systems have evolved from application specific accelerators to a general purpose computing paradigm. But the algorithmic techniques and software tools are also heavily based on the hardware paradigm from which they have evolved. Loop statements in traditional programs consist of regular, repetitive computations which are the most likely candidates for performance enhancement using configurable hardware. This paper develops a formal methodology for mapping loops onto reconfigurable architectures. We develop a parameterized abstract model of reconfigurable architectures which is general enough to capture a wide range of configurable systems. Our abstract model is used to define and solve the problem of mapping loop statements onto reconfigurable architectures. We show a polynomial time algorithm to compute the optimal sequence of configurations for one important variant of the problem. We illustrate our approach by showing the mapping of an example loop statement.

The performance requirements of applications have continuously superseded the computing power of architecture platforms. Increasingly larger number of transistors available on a chip have resulted in complex architectures and integration of various architecture components on the chip. But, the incremental performance gains obtained are lower as the complexity and the integration increase. Reconfigurable architectures can adapt the behavior of the hardware resources to a specific computation that needs to be performed. Computing using reconfigurable architectures provides an alternate paradigm to utilize the available logic resources on the chip. For several classes of applications, reconfigurable computing promises several orders of magnitude speed-up compared to conventional architectures. This article provides a brief insight into the architectures, models and algorithms which facilitate reconfigurable computing. 1 Introduction Microprocessors are at the heart of most curr...