The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. However, architects do not quantify the impact of these design decisions on the effort required to verify them, potentially increasing the time to market. We propose designing processors with formal verifiability as a first-class design constraint. Using Cadence SMV, a composite formal verification tool that combines model checking and theorem proving, we explore several aspects of processor design, including caches, TLBs, pipeline depth, ALUs, and bypass logic. We show that subtle differences in design decisions can lead to large

The cache coherence mechanisms are a key component towards achieving the goal of continuing exponential performance growth through widespread thread-level parallelism. This dissertation makes several contributions in the space of cache coherence for multicore chips. First, we recognize that rings are emerging as a preferred on-chip interconnect. Unfortunately a ring does not preserve the total order provided by a bus. We contribute a new cache coherence protocol that exploits a ring’s natural round-robin order. In doing so, we show how our new protocol achieves both fast performance and performance stability—a combination not found in prior designs. Second, we explore cache coherence protocols for systems constructed with several multicore chips. In these Multiple-CMP systems, coherence must occur both within a multicore chip and among multicore chips. Applying hierarchical coherence protocols greatly increases complexity, especially when a bus is not relied upon for the first-level of coherence. We first contribute a hierarchical coherence protocol, DirectoryCMP, that uses two directory-based protocols bridged together to create a highly scalable system. We then contribute TokenCMP, which extends token coherence, to create a Multiple-CMP system that is flat for correctness yet hierarchical for performance.

Modern computing systems are amazingly complicated artifacts. Today’s hardware and software systems combine billions of transistors and millions of lines of code to form the computational and communication infrastructure critical for commerce, government, education, and entertainment. Because of the increasing sophistication of these computing systems, creating correct, high-performance, robust, and secure systems has become an almost insurmountable challenge. One result of this trend is that the design and validation of both hardware and software is becoming more expensive and taking longer, yet buggy and insecure systems are still widespread. With the advent of ubiquitous multi-core chips, these systems are increasingly parallel and concurrent, adding design and validation complexity to already complex systems. Research agenda. My research focus is on practical techniques to meet the challenge of creating multi-core hardware and software systems that are correct, fast, robust, and secure. Towards this goal, I have been exploring two primary research thrusts to address different hardware and low-level software aspects of this larger problem. The first thrust is making multicore programming easier, which includes three concrete projects: (1) exploring the semantics and simple hardware implementation of transactional memory [1, 2, 3, 4], (2) programmer-friendly, adaptive, latency-tolerant, and verifiable

Power management is important for multicore architectures. One important challenge for multicore DPM schemes is verifying that they are both safe (cannot lead to power or thermal catastrophes) and efficient (achieve as much performance as possible without exceeding power constraints). The verification difficulty varies among designs, depending, for example, on the particular power management mechanisms utilized and the algorithms used to adjust them. However, verification effort is often not considered in the early stages of DPM scheme design, leading to proposals that can be extremely difficult to verify. To address this problem, we propose using formal verification (with probabilistic model checking) of a high-level, early-stage model of the DPM scheme. Using the model checker, we estimate the required verification effort, providing insight on how certain design parameters impact this effort. Furthermore, we supplement the verifiability results with high-level estimates of power consumption and performance, which allow us to perform a trade-off analysis between power, performance, and verification. We show that this trade-off analysis uncovers design points that are better than those that consider only power and performance. 1.

Lake Como, ItalyWelcome to the 3 rd Workshop on Dependable Architectures!

Performance enhancement for high speed computing can be carried out by using many techniques and architectures at software and high hardware level. Performance enhancement using hardware techniques may include the use of multiple computing nodes or a single node consisting of multiple processors. Symmetric multiprocessor is one of the modern architectures used to perform extensive computations. Symmetric multiprocessors have many configuration modes to carry out these heavy computations. The performance of Symmetric multiprocessors is analyzed and compared with high-fidelity models. Processors models are used to design and construct the architectures of symmetric multiprocessors. In this research paper such kind of critical design aspects of symmetric multi processors have been analyzed for further enhancement of