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14
Hardness of Approximate Twolevel Logic Minimization and PAC Learning with Membership Queries
 in Proceedings of the 38th Annual ACM Symposium on the Theory of Computing
, 2006
"... Producing a small DNF expression consistent with given data is a classical problem in computer science that occurs in a number of forms and has numerous applications. We consider two standard variants of this problem. The first one is twolevel logic minimization or finding a minimum DNF formula con ..."
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Producing a small DNF expression consistent with given data is a classical problem in computer science that occurs in a number of forms and has numerous applications. We consider two standard variants of this problem. The first one is twolevel logic minimization or finding a minimum DNF formula consistent with a given complete truth table (TTMinDNF). This problem was formulated by Quine in 1952 and has been since one of the key problems in logic design. It was proved NPcomplete by Masek in 1979. The best known polynomial approximation algorithm is based on a reduction to the SETCOVER problem and produces a DNF formula of size O(d · OPT), where d is the number of variables. We prove that TTMinDNF is NPhard to approximate within d γ for some constant γ> 0, establishing the first inapproximability result for the problem. The other DNF minimization problem we consider is PAC learning of DNF expressions when the learning algorithm must output a DNF expression as its hypothesis (referred to as proper learning). We prove that DNF expressions are NPhard to PAC learn properly even when the learner has access to membership queries, thereby answering a longstanding open question due to Valiant [40]. Finally, we provide a concrete connection between these variants of DNF minimization problem. Specifically, we prove that inapproximability of TTMinDNF implies hardness results for restricted proper learning of DNF expressions with membership queries even when learning with respect to the uniform distribution only.
Automating recursive Definitions and Termination Proofs in HigherOrder Logic
, 2009
"... The aim of this thesis is to provide an infrastructure for general recursive function definitions in a proof assistant based on higherorder logic (HOL) that has no native support for recursion or pattern matching. In the first part we develop a tool that automates recursive function definitions and ..."
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The aim of this thesis is to provide an infrastructure for general recursive function definitions in a proof assistant based on higherorder logic (HOL) that has no native support for recursion or pattern matching. In the first part we develop a tool that automates recursive function definitions and provides appropriate proof rules for them. Compared to previous work, our package supports the definition of partial functions, modeling the domain of the function by an inductive domain predicate. An automaticallygenerated partial induction rule makes partial correctness proofs independent from termination proofs. This modularity considerably facilitates termination arguments for nested recursions. The second part addresses the problem of automatically solving the termination proof obligations that arise from function definitions. Methods from the literature can be applied, but require significant adaptation to the specific needs of our setting: They must produce full formal proofs and work relative to a rich
Minimizing DNF Formulas and AC^0 Circuits Given a Truth Table
 IN PROCEEDINGS OF THE 21ST ANNUAL IEEE CONFERENCE ON COMPUTATIONAL COMPLEXITY
, 2006
"... For circuit classes R, the fundamental computational problem MinR asks for the minimum Rsize of a Boolean function presented as a truth table. Prominent examples of this problem include MinDNF, which asks whether a given Boolean function presented as a truth table has a kterm DNF, and MinCircu ..."
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For circuit classes R, the fundamental computational problem MinR asks for the minimum Rsize of a Boolean function presented as a truth table. Prominent examples of this problem include MinDNF, which asks whether a given Boolean function presented as a truth table has a kterm DNF, and MinCircuit (also called MCSP), which asks whether a Boolean function presented as a truth table has a size k Boolean circuit. We present a new reduction proving that MinDNF is NPcomplete. It is significantly simpler than the known reduction of Masek [30], which is from CircuitSAT. We then give a more complex reduction, yielding the result that MinDNF cannot be approximated to within a factor smaller than (logN) γ, for some constant γ> 0, assuming that NP is not contained in quasipolynomial time. The standard greedy algorithm for Set Cover is often used in practice to approximate MinDNF. The question of whether MinDNF can be approximated to within a factor of o(logN) remains open, but we construct an instance of MinDNF on which the solution produced by the greedy algorithm is Ω(logN) larger than optimal. Finally, we turn to the question of approximating circuit size for slightly more general classes of circuits. DNF formulas are depth two circuits of AND and OR gates. Depth d circuits are denoted by AC0 d. We show that it is hard to approximate the size of AC0 d circuits (for large enough d) under cryptographic assumptions.
Complexity of DNF Minimization and Isomorphism Testing for Monotone Formulas
, 2008
"... We investigate the complexity of finding prime implicants and minimum equivalent DNFs for Boolean formulas, and of testing equivalence and isomorphism of monotone formulas. For DNF related problems, the complexity of the monotone case differs strongly from the arbitrary case. We show that it is DPc ..."
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We investigate the complexity of finding prime implicants and minimum equivalent DNFs for Boolean formulas, and of testing equivalence and isomorphism of monotone formulas. For DNF related problems, the complexity of the monotone case differs strongly from the arbitrary case. We show that it is DPcomplete to check whether a monomial is a prime implicant for an arbitrary formula, but the equivalent problem for monotone formulas is in L. We show PPcompleteness of checking if the minimum size of a DNF for a monotone formula is at most k, and for k in unary, we show that the complexity of the problem drops to coNP. In [Uma01] a similar problem for arbitrary formulas was shown to be Σ p 2complete. We show that calculating the minimum equivalent DNF for a monotone formula is possible in outputpolynomial time if and only if P = NP. Finally, we disprove a conjecture from [Rei03] by showing that checking whether two formulas are isomorphic has the same complexity for arbitrary formulas as for monotone formulas.
Minimization for Generalized Boolean Formulas
 PROCEEDINGS OF THE TWENTYSECOND INTERNATIONAL JOINT CONFERENCE ON ARTIFICIAL INTELLIGENCE
"... The minimization problem for propositional formulas is an important optimization problem in the second level of the polynomial hierarchy. In general, the problem is Σ p 2complete under Turing reductions, but restricted versions are tractable. We study the complexity of minimization for formulas in ..."
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The minimization problem for propositional formulas is an important optimization problem in the second level of the polynomial hierarchy. In general, the problem is Σ p 2complete under Turing reductions, but restricted versions are tractable. We study the complexity of minimization for formulas in two established frameworks for restricted propositional logic: The Post framework allowing arbitrarily nested formulas over a set of Boolean connectors, and the constraint setting, allowing generalizations of CNF formulas. In the Post case, we obtain a dichotomy result: Minimization is solvable in polynomial time or coNPhard. This result also applies to Boolean circuits. For CNF formulas, we obtain new minimization algorithms for a large class of formulas, and give strong evidence that we have covered all polynomialtime cases.
EXOR Projected Sum of Products
, 2006
"... In this paper we introduce a new algebraic form for Boolean function representation, called EXORProjected Sum of Products (EPSOP), resulting in a four level network that can be easily implemented in practice. We prove that deriving an optimal EPSOP from an optimal SOP form is a hard problem (NP N ..."
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In this paper we introduce a new algebraic form for Boolean function representation, called EXORProjected Sum of Products (EPSOP), resulting in a four level network that can be easily implemented in practice. We prove that deriving an optimal EPSOP from an optimal SOP form is a hard problem (NP NPhard); nevertheless we propose a very efficient approximation algorithm, which returns in polynomial time an EPSOP form whose cost is guaranteed to be near the optimum. Experimental evidence shows that for about 35 % of the classical synthesis benchmarks the EPSOP networks have a smaller area and delay with respect to the optimal SOPs (sometimes gaining even 4050 % of the area). Since the computational times required are extremely short, we recommend the use of the proposed approach as a postprocessing step after SOP minimization.
1An FSM ReEngineering Approach to Sequential Circuit Synthesis by State Splitting
"... We propose Finite State Machine (FSM) reengineering, a performance enhancement framework for FSM synthesis and optimization. It starts with the traditional FSM synthesis procedure, then proceeds to reconstruct a functionally equivalent but topologically different FSM based on the optimization obj ..."
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We propose Finite State Machine (FSM) reengineering, a performance enhancement framework for FSM synthesis and optimization. It starts with the traditional FSM synthesis procedure, then proceeds to reconstruct a functionally equivalent but topologically different FSM based on the optimization objective, and concludes with another round of FSM synthesis on the reconstructed FSM. This approach explores a larger solution space that consists of a set of FSMs functionally equivalent to the original one, making it possible to obtain better solutions than in the original FSM. Guided by the result from the rst round of synthesis, the solution space exploration process can be rapid and costefcient. We apply this framework to FSM state encoding for power minimization and area minimization. The FSM is rst minimized and encoded using existing state encoding algorithms. Then we develop both a heuristic algorithm and a genetic algorithm to reconstruct the FSM. Finally, the FSM is reencoded by the same encoding algorithms. To demonstrate the effectiveness of this framework, we conduct experiments on MCNC91 sequential circuit benchmarks. The circuits are read in and synthesized in SIS environment. After FSM reengineering are performed, we measure the power, area and delay in the newly synthesized circuits. In the powerdriven synthesis, we observe an average 5.5 % of total power reduction with 1.3 % area increase and 1.3 % delay increase. This results are in general better than other low power state encoding techniques on comparable cases. In the areadriven synthesis, we observe an average 2.7 % area reduction, 1.8% delay reduction, and 0.4 % power increase. Finally, we use integer linear programming to obtain the optimal low power state encoding for benchmarks of small size. We nd that the optimal solutions in the re engineered FSMs are 1 % to 8% better than the optimal solutions in the original FSMs in terms of power minimization. I.
International Journal of Electrical and Computer Engineering 2:1 2007 Matrix Based Synthesis of EXOR dominated Combinational Logic for
"... Abstract — This paper discusses a new, systematic approach to the synthesis of a NPhard class of nonregenerative Boolean networks, described by F ON[F OFF]={m i}[{M i}], where for every m j[M j]∈{m i}[{M i}], there exists another m k[M k]∈{m i}[{M i}], such that their Hamming distance HD(m j, m k) ..."
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Abstract — This paper discusses a new, systematic approach to the synthesis of a NPhard class of nonregenerative Boolean networks, described by F ON[F OFF]={m i}[{M i}], where for every m j[M j]∈{m i}[{M i}], there exists another m k[M k]∈{m i}[{M i}], such that their Hamming distance HD(m j, m k)=HD(Mj, M k)=O(n), (where ‘n ’ represents the number of distinct primary inputs). The method automatically ensures exact minimization for certain important selfdual functions with 2 n1 points in its oneset. The elements meant for grouping are determined from a newly proposed weighted incidence matrix. Then the binary value corresponding to the candidate pair is correlated with the proposed binary value matrix to enable direct synthesis. We recommend algebraic factorization operations as a post processing step to enable reduction in literal count. The algorithm can be implemented in any high level language and achieves best cost optimization for the problem dealt with, irrespective of the number of inputs. For other cases, the method is iterated to subsequently reduce it to a problem of O(n1), O(n2),…. and then solved. In addition, it leads to optimal results for problems exhibiting higher degree of adjacency, with a different interpretation of the heuristic, and the results are comparable with other methods. In terms of literal cost, at the technology independent stage, the circuits synthesized using our algorithm enabled net savings over AOI (ANDORInvert) logic, ANDEXOR logic (EXOR SumofProducts or ESOP forms) and ANDOREXOR logic by 45.57%, 41.78 % and 41.78 % respectively for the various problems. Circuit level simulations were performed for a wide variety of case studies at 3.3V and 2.5V supply to validate the performance of the proposed method and the quality of the resulting synthesized circuits at two different voltage corners. Power estimation was carried out for a 0.35micron TSMC CMOS process technology. In comparison with AOI logic, the proposed method enabled mean savings in power by 42.46%. With respect to ANDEXOR logic, the proposed method yielded power savings to the tune of 31.88%, while in comparison with ANDOREXOR level networks; average power savings of 33.23 % was obtained.
Matrix Based Synthesis of EXOR Dominated . . .
"... This paper discusses a new, systematic approach to the synthesis of a NPhard class of nonregenerative Boolean networks, described by F ON[F OFF]={m i}[{M i}], where for every m j[M j]∈{m i}[{M i}], there exists another m k[M k]∈{m i}[{M i}], such that their Hamming distance HD(m j, m k)=HD(Mj, M ..."
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This paper discusses a new, systematic approach to the synthesis of a NPhard class of nonregenerative Boolean networks, described by F ON[F OFF]={m i}[{M i}], where for every m j[M j]∈{m i}[{M i}], there exists another m k[M k]∈{m i}[{M i}], such that their Hamming distance HD(m j, m k)=HD(Mj, M k)=O(n), (where ‘n ’ represents the number of distinct primary inputs). The method automatically ensures exact minimization for certain important selfdual functions with 2 n1 points in its oneset. The elements meant for grouping are determined from a newly proposed weighted incidence matrix. Then the binary value corresponding to the candidate pair is correlated with the proposed binary value matrix to enable direct synthesis. We recommend algebraic factorization operations as a post processing step to enable reduction in literal count. The algorithm can be implemented in any high level language and achieves best cost optimization for the problem dealt with, irrespective of the number of inputs. For other cases, the method is iterated to subsequently reduce it to a problem of O(n1), O(n2),…. and then solved. In addition, it leads to optimal results for problems exhibiting higher degree of adjacency, with a different interpretation of the heuristic, and the results are comparable with other methods. In terms of literal cost, at the technology independent stage, the circuits synthesized using our algorithm enabled net savings over AOI (ANDORInvert) logic, ANDEXOR logic (EXOR SumofProducts or ESOP forms) and ANDOREXOR logic by 45.57%, 41.78 % and 41.78 % respectively for the various problems. Circuit level simulations were performed for a wide variety of case studies at 3.3V and 2.5V supply to validate the performance of the proposed method and the quality of the resulting synthesized circuits at two different voltage corners. Power estimation was carried out for a 0.35micron TSMC CMOS process technology. In comparison with AOI logic, the proposed method enabled mean savings in power by 42.46%. With respect to ANDEXOR logic, the proposed method yielded power savings to the tune of 31.88%, while in comparison with ANDOREXOR level networks; average power savings of 33.23 % was obtained.