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A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware
- Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 2005. Pp
, 2005
"... This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Reconfigurable hardware devices are increasingly used in embedded systems. To utilize these devices also for systems with real-time constraints, predictable task scheduling is required. We fo ..."
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Cited by 12 (1 self)
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This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Reconfigurable hardware devices are increasingly used in embedded systems. To utilize these devices also for systems with real-time constraints, predictable task scheduling is required. We formalize the periodic task scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known Earliest Deadline First (EDF) technique to the FPGA execution model. Although the algorithm reveals good scheduling performance, it lacks an efficient schedulability test and requires a high number of FPGA configurations. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method is inferior to the EDF-based technique regarding schedulability, it comes with a fast schedulability test and greatly reduces the number of required FPGA configurations.
MCGREP–A Predictable Architecture for Embedded Real-Time Systems
- Proceedings of the 27th IEEE International Real-Time Systems Symposium
, 2006
"... Real-time systems design involves many important choices, including that of the processor. The fastest proces-sors achieve performance by utilizing architectural features that make them unpredictable, leading to difficulties prov-ing offline that application process deadlines will be met, in the wor ..."
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Cited by 11 (2 self)
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Real-time systems design involves many important choices, including that of the processor. The fastest proces-sors achieve performance by utilizing architectural features that make them unpredictable, leading to difficulties prov-ing offline that application process deadlines will be met, in the worst-case. Utilizing slower, more predictable pro-cessors, may not provide sufficient instruction throughput to execute all required application processes. This exposes a key trade-off in processor selection for real-time systems: predictability versus instruction throughput. This paper proposes MCGREP, a novel CPU architec-ture that combines predictability, high instruction through-put and flexibility. MCGREP is entirely microprogrammed, with multiple execution units. Basic operation involves im-plementation of a conventional set of CPU instructions in microcode- MCGREP then executes object code suitably compiled. Advanced operation allows the application to dynamically load new microcode, enabling new application specific instructions to increase overall performance. MCGREP is implemented upon reconfigurable logic (FPGA)- an increasingly important platform for the embed-ded RTS. Custom microcode configurations for new instruc-tions are generated from C source. MCGREP is shown to have performance comparable to two popular FPGA soft-core CPUs (OpenRISC and Microblaze, the latter a com-mercial product). Flexibility is demonstrated by implement-ing an existing instruction set (OpenRISC) in microcode, with application-specific instructions to improve overall performance. As a further demonstration, predictable two-level interrupt and synchronization mechanisms are pro-grammed in microcode. 1
M.: ReconOS: An RTOS supporting Hard- and Software Threads
- IEEE Int. Conf. on Field Programmable Logic and Applications
, 2007
"... Modern platform FPGAs integrate fine-grained reconfigur-able logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodologies have not kept up with the rise in complex-ity of the target hardware. In particular, there is little over-lap between ..."
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Cited by 10 (0 self)
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Modern platform FPGAs integrate fine-grained reconfigur-able logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodologies have not kept up with the rise in complex-ity of the target hardware. In particular, there is little over-lap between the programming model for embedded software running on a real-time operating system and the program-ming model for digital logic. In this paper, we present the operating system ReconOS which supports both software and hardware threads with a single unified programming model. ReconOS is based on eCos, a widely-used real-time operating system (RTOS). We investigate the incurred time and area overheads, espe-cially for inter-thread communication across the hardware/-software boundary, and present a case study demonstrating the feasibility of the RTOS-centric design approach. 1.
SystemCbased design methodology for reconfigurable systemon-chip
- In Digital System Design, 2005. Proceedings. 8th Euromicro Conference on
, 2005
"... Reconfigurable system is a promising alternative to deliver both flexibility and performance at the same time. New reconfigurable technologies and technology-dependent tools have been developed, but a system-level design methodology to support system analysis and fast design space exploration is mis ..."
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Cited by 8 (2 self)
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Reconfigurable system is a promising alternative to deliver both flexibility and performance at the same time. New reconfigurable technologies and technology-dependent tools have been developed, but a system-level design methodology to support system analysis and fast design space exploration is missing. In this paper, we present a SystemC-based system-level design approach. The main focuses are the resource estimation to support system analysis and reconfiguration modeling for fast performance simulation. The approach was applied in a real design case of a WCDMA detector on a commercially available reconfigurable platform. The run-time reconfiguration was used and the design showed 40 % area saving when compared to a functionally equivalent fixed system and 30 times better in processing time when compared to a functionally equivalent pure software design.
Design optimizations for tiled partially reconfigurable systems
- IEEE Trans. Very Large Scale Integr. (VLSI) Syst
"... Abstract—In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially recon ..."
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Cited by 7 (2 self)
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Abstract—In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially reconfigurable system requires additional design steps, such as partitioning the device resources into static and dynamic regions. We present the concept of tiled PR regions, which enables a flexible online-placement of PR modules. Dynamic reconfiguration requires a suitable communication infrastructure to interconnect the static and dynamic system components. We present an embedded communication macro, a communication infrastructure that interconnects PR modules in a tiled PR region. Efficient online-placement of PR modules depends not only on the placement algorithm, but also on design-time aspects such as the chosen synthesis regions of the PR modules. We propose a design method for selecting suitable synthesis regions for the PR modules aiming to optimize their placement at run-time. Index Terms—Communication macro, design automation, field-programmable gate arrays (FPGAs), overlap graph, reconfigurable architectures. I.
Hsiung: “Dynamically Swappable Hardware design in Partially Reconfigurable Systems”-
- In Proc. of the International Symposium on Circuits and Systems (ISCAS
, 2007
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Defragmenting the module layout of a partially reconfigurable device
- IN PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS (ERSA), LAS VEGAS
, 2005
"... Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, ma ..."
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Cited by 7 (0 self)
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Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by propose an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a twodimensional strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve two-dimensional defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances.
Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC
- in Proceedings of the International Conference on Embedded and Ubiquitous Computing
, 2005
"... Abstract. Existing operating systems can manage the execution of software tasks efficiently, however the manipulation of hardware tasks is very limited. In the research on the design and implementation of an embedded operating system that manages both software and hardware tasks in the same framewo ..."
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Cited by 6 (2 self)
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Abstract. Existing operating systems can manage the execution of software tasks efficiently, however the manipulation of hardware tasks is very limited. In the research on the design and implementation of an embedded operating system that manages both software and hardware tasks in the same framework, two major issues are the dynamic scheduling and the dynamic placement of hardware tasks into a reconfigurable logic space in an SoC. The distinguishing criteria for good dynamic scheduling and placement methods include the total schedule length and the amount of fragmentation incurred while tasks are dynamically placed and replaced. Existing methods either do not take fragmentation into consideration or postpone the consideration of fragmentation to a later stage of space allocation. In our method, we try to reduce fragmentation during placement itself. The advantage of such an approach is that not only the reconfigurable space is utilized more efficiently, but the total schedule length is also reduced, that is, hardware tasks complete faster. Experimental results on large random tasks sets have shown that the proposed improvement is as much as 23.3% in total fragmentation and 2.0% in total schedule time.
Adaptive allocation of software and hardware real-time tasks for FPGAbased embedded systems
- In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium
, 2006
"... Operating systems for reconfigurable devices enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks running on a reconfigurable hardware device (FPGA). Furthermore, in such systems relocatable tasks can be migrated from software to hardware ..."
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Cited by 6 (2 self)
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Operating systems for reconfigurable devices enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks running on a reconfigurable hardware device (FPGA). Furthermore, in such systems relocatable tasks can be migrated from software to hardware and viceversa. The combination of high performance and predictability of hardware execution with software flexibility makes such architecture especially suitable to implement high-performance real-time embedded systems. In this work, we first discuss design and scheduling issues for relocatable tasks. We then concentrate on the on-line admission control problem. Task allocation and migration between the CPU and the reconfigurable device is discussed and sufficient feasibility tests are derived. Finally, the effectiveness of our relocation strategy is shown through a series of synthetic simulations. 1
Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures
- ACM Trans. Reconfigurable Technol. Syst
, 2008
"... To cope with increasing demands for higher computational power and greater system flexibility, dynamically and partially reconfigurable logic has started to play an important role in embedded systems and systems-on-chip (SoC). However, when using traditional design methods and tools, it is difficult ..."
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Cited by 6 (0 self)
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To cope with increasing demands for higher computational power and greater system flexibility, dynamically and partially reconfigurable logic has started to play an important role in embedded systems and systems-on-chip (SoC). However, when using traditional design methods and tools, it is difficult to estimate or analyze the performance impact of including such reconfigurable logic devices into a system design. In this work, we present a system-level framework, called Perfecto, which is able to perform rapid exploration of different reconfigurable design alternatives and to detect system performance bottlenecks. This framework is based on the popular IEEE standard system-level design language SystemC, which is supported by most EDA and ESL tools. Given an architecture model and an application model, Perfecto uses SystemC transaction-level models (TLMs) to simulate the system design alternatives automatically. Different hardware-software copartitioning, coscheduling, and placement algorithms can be embedded into the framework for analysis; thus, Perfecto can also be used to design the algorithms to be used in an operating system for reconfigurable systems. Applications to a simple illustration example and a network security system have shown how Perfecto helps a designer make intelligent partition decisions, optimize system performance, and evaluate task placements.
