A novel, hybrid number representation is proposed in this paper. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several static CMOS implementations of a two--operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the tradeoffs between area and execution time associated with each of the possible repre...

We propose an asymmetric high-radix signed-digit (AHSD) number system for fast binary addition, and show that the AHSD number system supports carry-free (CF) addition. The CF additions in AHSD, to be classified as quasi-closed and subclosed additions, use only one redundant digit for any radix r ≥ 2. Novel algorithms for constructing the three-stage CF adder (CFA) based on the AHSD number system are also presented. Moreover, if the radix is specified as r = 2 m, where m is any positive integer, the binary-to-AHSD conversion can be done in constant time regardless of the word-length. Hence, the AHSD-to-binary conversion dominates the performance of an AHSD-based arithmetic system. We also propose two efficient algorithms for converting AHSD numbers to binary format. The first uses a novel structure to achieve high speed, while the second uses simple transformations and conventional additions to provide hardware reusability. These results are important since the conversion from AHSD numbers to binary format has been considered the performance bottleneck of AHSD-based arithmetic systems.

This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from W t fa to W tmux where t fa and tmux , respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carrygeneration component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W , is a power of two, then all carry signals can be generated in log2W tmux time using W (log2W \Gamma 1)+1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (W l...

this paper all possible two-bit encodings for the intermediate variables and identify the ones that enable multiplexor-based implementations. Some of these encodings enable further simplification of the multiplexor-based realizations. Our analysis also shows that adopting an intermediate signed-digit representation simply amounts to selecting one of the possible encodings. Thus, there is no inherent advantage to the use of intermediate signed-digit representations in a two operand addition. Finally, we extend our analysis to the generalized look-ahead-recursions proposed by Doran

A new implementation for minimally redundant radix-4 floating-point SRT division/square-root (division/sqrt) with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the magnitude of the quotient (root) digit is calculated by comparing the truncated partial remainder with 2 limited precision multiples of the divisor (partial root). The digit sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using the logical synthesis (Synopsys DC with Artisan 0.18 µm typical library) shows a latency of 2.5 ns for the recurrence of the proposed division/sqrt. This is less than of the conventional implementation.

The equivalence between redundant-binary to twos-complement number conversionand twos-complement addition is shown using a simple transform between the two number domains. As a consequence, all hardware architectures designed for eitheroperation may be easily adapted to implement the other.

Abstract: Speed of digital arithmetic processor depends mainly on the speed of adders. This paper provides a technique so that we can increase the speed of addition. Hybrid signed digit number representation perform addition in such a way that the carry propagation chain is limited to single digit position and hence are used to speed up arithmetic operation. Also hybrid signed digit reduces the critical path delay by parallelizing. Hybrid signed digit can be appropriate to use, when output is redundant representation.