Traditionally, VLSI architects and designers have acknowledged the area, performance, and effort tradeoffs between cell-based and full-custom implementations of the same datapath function. However, few attempts have been made to characterize these tradeoffs in the context of contemporary fabrication processes and area place and route tools. More importantly, few attempts have been made to determine how to enable cell-based implementations to approach the density and speed of full-custom designs. This work quantifies the limits of cell-based datapath implementations based on results derived from a detailed analysis of the density and performance tradeoffs in the implementation of two full-custom datapaths, the Integer Register-Read Datapath (IRRDP) and the 64-bit adder/subtracter (ADDSUB), employed in the multi-ALU Processor (MAP) chip. A cell-based implementation of the IRRDP is 1.64x larger than the full-custom original. The critical timing path for the cell-based implementation is 11...