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Address register allocation for arrays in loops of embedded programs
- Microelectronics Journal
, 1009
"... Efficient address register allocation has been shown to be a central problem in code generation for processors with restricted addressing modes. This paper extends previous work on Global Array Reference Allocation (GARA), the problem of allocating address registers to array references in loops. It ..."
Abstract
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Cited by 1 (1 self)
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Efficient address register allocation has been shown to be a central problem in code generation for processors with restricted addressing modes. This paper extends previous work on Global Array Reference Allocation (GARA), the problem of allocating address registers to array references in loops. It describes two heuristics to the problem, presenting experimental data to support them. In addition, it proposes an approach to solve GARA optimally which, albeit computationally exponential, is useful to measure the efficiency of other methods. Experimental results, using the MediaBench benchmark and profiling information, reveal that the proposed heuristics can solve the majority of the benchmark loops near optimality in polynomial-time. A substantial execution time speedup is reported for the benchmark programs, after compiled with the original and the optimized versions of GCC.
Register Allocation for Indirect Addressing in Loops
, 1998
"... Syntax tree corresponding to an array reference is not decomposed into its atomic operations. In other words, the references to array elements are maintained until the final schedule is performed in the program. Assume also that Common Subexpression Elimination (CSE) is not allowed for array indices ..."
Abstract
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Syntax tree corresponding to an array reference is not decomposed into its atomic operations. In other words, the references to array elements are maintained until the final schedule is performed in the program. Assume also that Common Subexpression Elimination (CSE) is not allowed for array indices, and that induction variable elimination is used to optimize the loop. Induction variable elimination is an important loop optimization based on strength reduction and code motion [Aho et al. 1988]. Consider for example array reference vector[i*a + k]. After induction variable elimination is performed, the array element address can be computed simply by adding a to register AR, which is initialized to &vector[0] + k and hoisted outside the loop. In the case of auto-increment (decrement), i.e. a = 1, the AGU automatically increments AR. When multidimensional array references are present within nested loops, references can usually be reduced to the simple unidimensional case (through inducti...
Algorithms for Array Reference Allocation in Loops of Embedded Programs
, 2002
"... Ecient address register allocation has been shown to be a central problem in code generation for processors with restricted addressing modes. This paper extends previous work on Global Array Reference Allocation (GARA), the problem of allocating address registers to array references in loops. It ..."
Abstract
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Ecient address register allocation has been shown to be a central problem in code generation for processors with restricted addressing modes. This paper extends previous work on Global Array Reference Allocation (GARA), the problem of allocating address registers to array references in loops. It describes two heuristics to the problem, based on the SSA Form, presenting experimental data to support them. In addition, it proposes an approach to solve GARA optimally which, albeit computationally exponential, is useful to measure the eciency of other methods. Experimental results, using the MediaBench benchmark, reveal that the proposed heuristics can solve the majority of the benchmark loops near optimality in polynomial-time. A substantial execution time speedup is reported for the benchmark programs, after compiled with the original and the optimized versions of GCC.

