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Adaptive Eager Boolean Encoding for Arithmetic Reasoning in Verification
, 2005
"... senting the official policies, either expressed or implied, of any sponsoring institution, the U.S. Government, or any other entity. ..."
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Cited by 9 (1 self)
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senting the official policies, either expressed or implied, of any sponsoring institution, the U.S. Government, or any other entity.
Modeling and verifying circuits using generalized relative timing
- In 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC
, 2005
"... We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using general ..."
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Cited by 4 (3 self)
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We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using generalized relative timing constraints are formally encoded as timed automata. Novel fully symbolic verification algorithms for timed automata are then used to either verify a temporal logic property or to check conformance against an untimed specification. The combination of our new modeling technique with fully symbolic verification methods enables us to verify larger circuits than has been possible with other approaches. We present case studies to demonstrate our approach, including a self-timed circuit used in the integer unit of the Intel R Pentium R 4 processor.
Partial order reduction for detecting safety and timing failures of timed circuits
- IEICE Trans. Inf. & Syst
, 2005
"... Abstract. This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original ..."
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Abstract. This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical verification. Experimenting with the STARI circuits, the proposed approach shows its effectiveness. 1
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method ∗
"... Using a level-oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model datapath circuits. On the other hand, in order to use such a model on large circuits, techniques to avoid the state explosion problem must ..."
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Using a level-oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model datapath circuits. On the other hand, in order to use such a model on large circuits, techniques to avoid the state explosion problem must be developed. This paper first introduces a level-oriented formal model based on time Petri nets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the correctness of the verification. Key words Level-oriented model, timed asynchronous circuits, formal verification, time Petri nets. 1
unknown title
"... Abstract We propose a novel technique for modeling and verify-ing timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can ex-press not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeledusi ..."
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Abstract We propose a novel technique for modeling and verify-ing timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can ex-press not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeledusing generalized relative timing constraints are formally encoded as timed automata. Novel fully symbolic verifica-tion algorithms for timed automata are then used to either verify a temporal logic property or to check confor-mance against an untimed specification. The combination of our new modeling technique with fully symbolic verifica-tion methods enables us to verify larger circuits than has been possible with other approaches. We present case stud-ies to demonstrate our approach, including a self-timed circuit used in the integer unit of the Intel R fl Pentium Rfl4 processor.
Approved for the Major Department
, 2004
"... committee and by majority vote has been found to be satisfactory. ..."
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A Compositional Approach to Asynchronous Design Verification with Automated State Space Reduction
, 2007
"... Productivity. This thesis is also based upon work supported by the National Science Foun-dation under grant No. 0546492. I am thankful for this generous funding. I extend my most sincere thanks to Dr. Zheng for introducing me to such a fascinating topic. He has provided wonderful support, guidance, ..."
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Productivity. This thesis is also based upon work supported by the National Science Foun-dation under grant No. 0546492. I am thankful for this generous funding. I extend my most sincere thanks to Dr. Zheng for introducing me to such a fascinating topic. He has provided wonderful support, guidance, and funding throughout this thesis. I would also like to thank Dr. Katkoori and Dr. Rundus for being on my committee and providing valuable
