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16
Relative timing
 IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, 2003
"... Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (CElement, FIFO, and RAPPID Tag Unit), facilitating transformations from speedindependent circuits to burstmode, relative timed, and pulsemode circuits. Relative t ..."
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Cited by 39 (17 self)
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Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (CElement, FIFO, and RAPPID Tag Unit), facilitating transformations from speedindependent circuits to burstmode, relative timed, and pulsemode circuits. Relative timing enables improved performance, area, power and testability in all three cases. 1.
Verification of analog/mixedsignal circuits using labeled hybrid petri nets
 IN: PROC. OF ICCAD
, 2006
"... System on a chip design results in the integration of digital, analog, and mixedsignal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling s ..."
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Cited by 24 (10 self)
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System on a chip design results in the integration of digital, analog, and mixedsignal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling such a heterogeneous set of components. This paper also describes a compiler from VHDLAMS to LHPNs. To support formal verification, this paper presents an efficient zonebased state space exploration algorithm for LHPNs. This algorithm uses a process known as warping to allow zones to describe continuous variables that may be changing at variable rates. Finally, this paper describes the application of this algorithm to a couple of analog/mixedsignal circuit examples.
Verification of Timed Circuits with Symbolic Delays
 In Proc. of Asia and South Pacific Design Automation Conference
, 2003
"... When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the verification problem becomes even more difficult. This paper presents a formal verification technique for timed circuits w ..."
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Cited by 11 (3 self)
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When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the verification problem becomes even more difficult. This paper presents a formal verification technique for timed circuits with symbolic delays. The approach is able to provide a set of sufficient linear constraints on the symbols that guarantee the correctness of the circuit. The applicability of the technique is shown by solving the problem of automatic discovery of linear constraints on input and gate delays that guarantee the correct behavior of asynchronous circuits.
Improved POSET timing analysis in Timed Petri Nets
 in Proceedings of International Workshop on Synthesis and System Integration of Mixed Technologies
, 2001
"... Abstract—This paper presents an improved timing algorithm for the analysis of timed Petri nets that is based on the POSET algorithm. The new algorithm reduces the number of redundant concurrent orderings the POSET algorithm explores by directly considering causal assignments. This paper shows that t ..."
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Cited by 9 (8 self)
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Abstract—This paper presents an improved timing algorithm for the analysis of timed Petri nets that is based on the POSET algorithm. The new algorithm reduces the number of redundant concurrent orderings the POSET algorithm explores by directly considering causal assignments. This paper shows that the new algorithm, when compared to the original POSET algorithm, results in an average 2.25 times improvement in runtime and a 57 % reduction in stored zones when applied to a suite of example circuits. Although the new algorithm can suffer an exponential increase in the number of causal assignments it must consider, this paper shows it to be a property of the POSET algorithm itself that does not happen often in practice. I.
Verification of concurrent systems with parametric delays using octahedra
 In ACSD ’05. IEEE Computer Society
, 2005
"... A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, the analysis computes automatically a set of constraints on the parameters s ..."
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Cited by 9 (1 self)
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A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, the analysis computes automatically a set of constraints on the parameters sufficient to guarantee the property. The main contribution is an innovative representation of the parametric timed state space based on bitvectors. Experimental results from the domain of timed circuits show that this representation improves both CPU time and memory usage with respect to another parametric approach, convex polyhedra. 1.
Correctness and Reduction in Timed Circuit Analysis
, 2002
"... To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these de ..."
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Cited by 9 (1 self)
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To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these designs, and algorithms to verify timing constraints are required to make them practical in commercial applications. Due to the complexity of the constraints, however, traditional static timing analysis is not adequate. Timed state space analysis is required; thus, improved timed state space analysis is paramount to producing efficient timed circuits. This diss
Verification of timed circuits with failure directed abstractions
 In 21st International Conference on Computer Design (ICCD
, 2003
"... Abstract — This paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not ..."
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Cited by 7 (4 self)
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Abstract — This paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not occur. To each subproblem, abstraction is applied using safe transformations to reduce the complexity of verification. The abstraction preserves all essential behaviors conservatively for the specific failure model in the concrete description. Therefore, no violations of the given failure model are missed when only the abstract description is error trace to either find a concrete error trace or report that it is a false negative. This paper presents results using the proposed failure directed abstractions as applied to several large timed circuit designs. Index Terms — timed circuits, formal verification, abstraction. I.
Timing analysis of an embedded memory: SPSMALL
 In 10th WSEAS International Conference on Circuits
, 2006
"... Abstract: This paper proposes a highlevel formalism, called Abstract Functional and Timing Graph (AFTG), for describing a memory architecture, which combines logical functionality and timing. After translation of the AFTG into the form a timed automaton, we are able to compute the response times of ..."
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Cited by 6 (5 self)
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Abstract: This paper proposes a highlevel formalism, called Abstract Functional and Timing Graph (AFTG), for describing a memory architecture, which combines logical functionality and timing. After translation of the AFTG into the form a timed automaton, we are able to compute the response times of the modeled memory, and check their consistency with the values specified in the datasheet. We also address the problem of finding optimal values of setup timings.
Verification of parametric timed circuits using octahedra
 In Designing correct circuits, DCC’04
, 2004
"... ..."
Hazard Checking of Timed Asynchronous Circuits Revisited
"... This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion, or efficient algorithms which use a (conservative) approximation to avoid statespace explosion but can result in the r ..."
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This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion, or efficient algorithms which use a (conservative) approximation to avoid statespace explosion but can result in the rejection of designs which are valid. In particular, [7] presents a timed extention of the work in [1] which is very efficient but is not able to handle circuits with internal loops, which prevents its use in some cases. We propose a new approach to the problem in order to overcome the mentioned limitations, without sacrificing efficiency. To do so, we first introduce a general framework targeted at the conservative checking of safety failures. This framework is not restricted to the checking of timed asynchronous circuits. Secondly, we propose a new (conservative) semantics for timed circuits, in order to use the proposed framework for hazard checking of such circuits. Using this framework with the proposed semantics yields an efficient algorithm that addresses the limitations of the previous approaches. 1