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Verification of analog/mixedsignal circuits using labeled hybrid petri nets
 IN: PROC. OF ICCAD
, 2006
"... System on a chip design results in the integration of digital, analog, and mixedsignal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling s ..."
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Cited by 24 (10 self)
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System on a chip design results in the integration of digital, analog, and mixedsignal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling such a heterogeneous set of components. This paper also describes a compiler from VHDLAMS to LHPNs. To support formal verification, this paper presents an efficient zonebased state space exploration algorithm for LHPNs. This algorithm uses a process known as warping to allow zones to describe continuous variables that may be changing at variable rates. Finally, this paper describes the application of this algorithm to a couple of analog/mixedsignal circuit examples.
Verification of Analog and MixedSignal Circuits Using Symbolic Methods
, 2007
"... Abstract. Embedded systems are composed of a heterogeneous collection of digital, analog, and mixedsignal hardware components. This paper presents a method for the verification of systems composed of such a variety of components. This method utilizes a new model, timed hybrid Petri nets (THPN), to ..."
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Cited by 18 (6 self)
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Abstract. Embedded systems are composed of a heterogeneous collection of digital, analog, and mixedsignal hardware components. This paper presents a method for the verification of systems composed of such a variety of components. This method utilizes a new model, timed hybrid Petri nets (THPN), to model these circuits. In particular, this paper describes an efficient, approximate algorithm to find the reachable states of a THPN model. Using this state space, desired properties specified in ACTL are verified. To demonstrate these methodologies, a few hybrid automata benchmarks, a tunnel diode oscillator, and a phaselocked loop are modeled and analyzed using THPNs. 1
Timed circuits: A new paradigm for highspeed design
 in Proc. of Asia and South Pacific Design Automation Conference
, 2001
"... Abstract — In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as selfresetting or delayedreset domino circuits used in IBM’s gigahertz processor (GUTS) and asynchronous circuits used in Intel’s RAPPID instruction length deco ..."
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Cited by 17 (12 self)
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Abstract — In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as selfresetting or delayedreset domino circuits used in IBM’s gigahertz processor (GUTS) and asynchronous circuits used in Intel’s RAPPID instruction length decoder. These new timed circuit styles, however, cannot be efficiently and accurately analyzed using traditional static timing analysis methods. This lack of efficient analysis tools is one of the reasons for the lack of mainstream acceptance of these design styles. This paper discusses several industrial timed circuits and gives an overview of our timed circuit design methodology. I.
Timed Circuit Verification Using TEL Structures
 IEEE Transactions on ComputerAided Design of Integrated Circuits
, 2001
"... Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In ord ..."
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Cited by 16 (6 self)
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Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gatelevel circuits. It also presents an algorithm based on partially ordered sets to make the statespace exploration of TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gatelevel timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance. I.
Modular Verification of Timed Circuits using Automatic Abstraction
 IEEE Transactions on ComputerAided Design
, 2003
"... Abstract — The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into modules, each with constrained complexity ..."
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Cited by 12 (8 self)
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Abstract — The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into modules, each with constrained complexity. Before verification is applied to each individual module, irrelevant information to the behavior of the selected module is abstracted away. This approach converts a verification problem with big exponential complexity to a set of subproblems, each with small exponential complexity. Experimental results are promising in that they indicate that our approach has the potential of completing much faster while using less memory than traditional flat analysis. Index Terms — timed circuits, modular verification, abstraction. I.
Improved POSET timing analysis in Timed Petri Nets
 in Proceedings of International Workshop on Synthesis and System Integration of Mixed Technologies
, 2001
"... Abstract—This paper presents an improved timing algorithm for the analysis of timed Petri nets that is based on the POSET algorithm. The new algorithm reduces the number of redundant concurrent orderings the POSET algorithm explores by directly considering causal assignments. This paper shows that t ..."
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Cited by 9 (8 self)
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Abstract—This paper presents an improved timing algorithm for the analysis of timed Petri nets that is based on the POSET algorithm. The new algorithm reduces the number of redundant concurrent orderings the POSET algorithm explores by directly considering causal assignments. This paper shows that the new algorithm, when compared to the original POSET algorithm, results in an average 2.25 times improvement in runtime and a 57 % reduction in stored zones when applied to a suite of example circuits. Although the new algorithm can suffer an exponential increase in the number of causal assignments it must consider, this paper shows it to be a property of the POSET algorithm itself that does not happen often in practice. I.
Correctness and Reduction in Timed Circuit Analysis
, 2002
"... To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these de ..."
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Cited by 9 (1 self)
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To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these designs, and algorithms to verify timing constraints are required to make them practical in commercial applications. Due to the complexity of the constraints, however, traditional static timing analysis is not adequate. Timed state space analysis is required; thus, improved timed state space analysis is paramount to producing efficient timed circuits. This diss
Verification of timed circuits with failure directed abstractions
 In 21st International Conference on Computer Design (ICCD
, 2003
"... Abstract — This paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not ..."
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Cited by 7 (4 self)
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Abstract — This paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not occur. To each subproblem, abstraction is applied using safe transformations to reduce the complexity of verification. The abstraction preserves all essential behaviors conservatively for the specific failure model in the concrete description. Therefore, no violations of the given failure model are missed when only the abstract description is error trace to either find a concrete error trace or report that it is a false negative. This paper presents results using the proposed failure directed abstractions as applied to several large timed circuit designs. Index Terms — timed circuits, formal verification, abstraction. I.
Modular Synthesis And Verification Of Timed Circuits Using Automatic Abstraction
"... In order to increase performance, circuit designers are beginning to use more aggressive timed circuit designs instead of traditional synchronous static logic designs. Recent design examples have shown that signi cant performance gains are achieved when these aggressive circuit styles are used. Corr ..."
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Cited by 3 (0 self)
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In order to increase performance, circuit designers are beginning to use more aggressive timed circuit designs instead of traditional synchronous static logic designs. Recent design examples have shown that signi cant performance gains are achieved when these aggressive circuit styles are used. Correct operation of these aggressive circuit styles is critically dependent on timing, and in industry they are typically designed by hand. To synthesize and verify timed circuits, the reachable state space of the circuit under the timing constraints needs to be explored. However, complete state space exploration is an exponential problem. State space explosion limits timed circuit designs to small sizes.
Time Separation of Events: An Inverse Method
, 2007
"... Abstract. The problem of “time separation ” can be stated as follows: Given a system made of several connected components, each one entailing a local delay known with uncertainty, what is the maximum time for traversing the global system? This problem is useful, e.g. in the domain of digital circuit ..."
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Cited by 3 (3 self)
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Abstract. The problem of “time separation ” can be stated as follows: Given a system made of several connected components, each one entailing a local delay known with uncertainty, what is the maximum time for traversing the global system? This problem is useful, e.g. in the domain of digital circuits, for determining the global traversal time of a signal from the knowledge of bounds on the component propagation delays. The uncertainty on each component delay is given under the form of an interval. The general problem is NPcomplete. We focus here on the inverse problem: we seek a set of intervals for the component delays for which the global traversal time is guaranteed to be no greater than a specified maximum. We give a polynomial time method to solve it. As a typical application, we show how to use the method in order to relax some specified local delays while preserving the maximum traversal time. This is especially useful, in the area of digital circuits, for optimizing “setup” timings of input signals (minimum timings required for stability). 1