Placement-driven technology mapping for LUT-based FPGAs (2003)

by J Lin, A Jagannathan, J Cong
Venue:in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays
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Heuristics for area minimization in LUT-based FPGA technology mapping

by Valavan Manohararajah, Stephen D. Brown, Zvonko G. Vranesic - Proc. IWLS ’04 , 2004
"... In this paper, an iterative technology mapping tool called IMap is presented. It supports depth-oriented (area is a secondary objective), area-oriented (depth is a secondary objective), and duplication-free mapping modes. The edge delay model, as opposed to the more common unit delay model, is used ..."
Abstract - Cited by 25 (5 self) - Add to MetaCart
In this paper, an iterative technology mapping tool called IMap is presented. It supports depth-oriented (area is a secondary objective), area-oriented (depth is a secondary objective), and duplication-free mapping modes. The edge delay model, as opposed to the more common unit delay model, is used throughout. Two new heuristics are used to obtain area reductions over previously published methods. The first heuristic predicts the effects of various mapping decisions on the area of the final solution and the second heuristic bounds the depth of the mapping solution at each node. In depth-oriented mode, when targeting 5-LUTs, IMap obtains depth optimal solutions that are 13.3 % and 12.5 % smaller than those produced by CutMAP and FlowMAP-r0, respectively. Targetting the same LUT size in area-oriented mode, IMap obtains solutions that are 13.7 % smaller than those produced by duplication-free mapping. 1.
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Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization

by Joey Y. Lin - In Proceedings of the conference on design automation , 2006
"... Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry out these two synthesis steps sequentially. Such a two-step approach cannot guarantee that the final delay of the circuit ..."
Abstract - Cited by 11 (0 self) - Add to MetaCart
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry out these two synthesis steps sequentially. Such a two-step approach cannot guarantee that the final delay of the circuit is optimal, because the quality of clustering depends significantly on the initial mapping result. To address this problem, we develop an algorithm that performs mapping and clustering simultaneously and optimally under a widely used clustering delay model. To our knowledge, our algorithm, named SMAC (simultaneous mapping and clustering) is the first delay-optimal algorithm to generate a synthesis solution that considers a combination of both steps. Compared to a synthesis flow using state-of-the-art mapping and clustering algorithms DAOmap [7] + T-VPACK [17] ― SMAC achieves a 25% performance gain with a 22 % area overhead under the clustering delay model. After placement and routing, SMAC is 12 % better in performance.
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An efficient technology mapping algorithm targeting routing congestion under delay constraints

by Rupesh S. Shelar, Xinning Wang - in Proc. ISPD , 2005
"... Routing congestion has become a serious concern in today’s VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestio ..."
Abstract - Cited by 7 (1 self) - Add to MetaCart
Routing congestion has become a serious concern in today’s VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delayoptimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows by 44%, on an average, as compared to the conventional technology mapping while satisfying delay constraints.
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Post-Placement Functional Decomposition for FPGAs

by Valavan Manohararajah, P. Singh, Stephen D. Brown, Zvonko G. Vranesic - In Proceedings of the International Workshop on Logic Synthesis , 2004
"... This work explores the effect of adding a simple functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has com-pleted, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circu ..."
Abstract - Cited by 5 (5 self) - Add to MetaCart
This work explores the effect of adding a simple functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has com-pleted, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decomposi-tions found. Any placement illegalities introduced by the new decompositions are resolved by an incremental place-ment step. Experiments conducted on Altera’s Stratix chips indicate that this functional decomposition technique can provide a performance improvement of 7.6 % on average, and up to 26.3 % on a set of industrial designs. 1.
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Timing Driven Functional Decomposition for FPGAs

by Valavan Manohararajah, P. Singh, Stephen D. Brown - In Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, CA , 2005
"... This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed ..."
Abstract - Cited by 3 (3 self) - Add to MetaCart
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decompositions found. Any placement illegalities introduced by the new decompositions are resolved by an incremental placement step. Experiments conducted on Altera’s Stratix and Stratix II device families indicate that this functional decomposition technique can provide average performance improvements of 6.1 % and 5.6 % on a large set of industrial designs, respectively. 1.
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Incremental Physical Resynthesis for Timing Optimization

by Peter Suaris, Lungtien Liu, Yuzheng Ding, Nanchi Chou - in The Twelfth Annual ACM International Symposium on FieldProgrammable Gate Arrays (FPGA ’04 , 2004
"... This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and physical optimizations without incurring unmanageable runtime complexity. Unlike previous approaches to this problem which ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and physical optimizations without incurring unmanageable runtime complexity. Unlike previous approaches to this problem which limit the types of operations and/or architectural features, we take advantage of many architectural characteristics of modern FPGA devices, and utilize many types of optimizations including cell repacking, signal rerouting, resource retargeting, and logic restructuring, accompanied by efficient incremental placement, to gradually transform a design via a series of localized logic and physical optimizations that verifiably improve overall compliance with timing constraints. This procedure works well on small and large designs, and can be administered through either an automatic optimizer, or an interactive user interface. Our preliminary experiments showed that this approach is very effective in fixing or reducing timing violations that cannot be reduced by other optimization techniques: For a set of test cases to which this is applicable, the worst timing violation is reduced by an average of 42.8%.
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Simultaneous Technology Mapping and Placement for Delay Minimization

by Yifang Liu, Rupesh S. Shelar, Jiang Hu - IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2011
"... Technology mapping and placement have a significant impact on delays in standard cell-based very large scale integrated circuits. Traditionally, these steps are applied separately to optimize the delays, possibly since efficient algorithms that allow the simultaneous exploration of the mapping and ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
Technology mapping and placement have a significant impact on delays in standard cell-based very large scale integrated circuits. Traditionally, these steps are applied separately to optimize the delays, possibly since efficient algorithms that allow the simultaneous exploration of the mapping and placement solution spaces are unknown. In this paper, we present an exact polynomial time algorithm for delay-optimal placement of a tree and extend the same to simultaneous technology mapping and placement for the optimal delay in the tree. We extend the algorithm by employing Lagrangian relaxation technique, which assesses the timing criticality of paths beyond a tree, to optimize the delays in directed acyclic graphs. Experimental results on benchmark circuits in a 70 nm technology show that our algorithms improve timing significantly with remarkably less runtimes compared to a competitive approach of iterative conventional timing-driven mapping and multilevel placement.

POST-PLACEMENT BDD-BASED DECOMPOSITION FOR FPGAS

by Valavan Manohararajah, P. Singh, Stephen D. Brown
"... This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decompositions found. Any placement illegalities introduced by the new decompositions are resolved by an incremental placement step. Experiments conducted on Altera’s Stratix and Stratix II device families indicate that this functional decomposition technique can provide average performance improvements of 6.1 % and 5.6 % on a large set of industrial designs, respectively. 1.
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Delay-Optimal Simultaneous Technology Mapping and Placement with Applications to Timing Optimization

by Yifang Liu, Rupesh S. Shelar, Jiang Hu - Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design , 2008
"... Abstract — Technology mapping and placement have significant impact on the delays in standard cell based very large scale integrated (VLSI) circuits. Traditionally, these steps are applied separately to optimize delays, possibly since efficient algorithms that allow the simultaneous exploration of t ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract — Technology mapping and placement have significant impact on the delays in standard cell based very large scale integrated (VLSI) circuits. Traditionally, these steps are applied separately to optimize delays, possibly since efficient algorithms that allow the simultaneous exploration of the mapping and placement solution spaces are unknown. In this paper, we present an exact polynomial time algorithm for delay-optimal placement of a tree and extend the same to simultaneous technology map-ping and placement for optimal delay in the tree. We extend the algorithm by employing Lagrangian relaxation technique, which assesses the timing criticality of paths beyond a tree, to optimize the delays in directed acyclic graphs (DAGs). Experimental results on benchmark circuits in a 70 nm technology show that our algorithms improve timing significantly with remarkably less run-times compared to a competitive approach of iterative conventional timing driven mapping and multi-level placement.
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Automated conversion from LUT-based . . .

by Francisco Javier Veredas Ramirez , 2007
"... Field-programmable gate-arrays (FPGAs) are used for application-specific stan-dard product (ASIC) prototyping or small volume products. In medium to large volume products, the prototyping design or the small volume product is converted to another integrated circuit (IC) structure such as mask-progr ..."
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Field-programmable gate-arrays (FPGAs) are used for application-specific stan-dard product (ASIC) prototyping or small volume products. In medium to large volume products, the prototyping design or the small volume product is converted to another integrated circuit (IC) structure such as mask-programmable gate arrays (MPGAs). MPGAs are of growing importance because of the increase of design cost, and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated FPGA prototype-design into an MPGA. The MPGA design uses potentially less area, delay, and dynamic power consumption than the FPGA design. In a conversion from an FPGA design, the engineer looks for a simple flow to minimize time-to-market. It is well known that the most time consuming process in an IC design is verification. Formal verification checks the functionality