In multiprocessors, caching is an effective latency reducing technique. However, adding caches to a multiprocessor system also introduces the cache coherence problem. Many different solutions to this problem have been proposed and implemented. This work focuses on the design of hardware controllers that enforce cache coherence, enable non-coherent operations, uncached operations and special functions in the NUMAchine multiprocessor. The controller logic is functionally decomposed into simpler components which enables an efficient and flexible implementation in field-programmable devices (FPDs). The controllers have been built and tested to run at a clock rate of 50 MHz. This implementation of hardware cache coherence provides a good trade-off between cost, flexibility and performance, placing it between implementations using custom hardware and those using commodity parts. iii Acknowledgements I would like to thank my supervisors Dr. Z. G. Vranesic and Dr. S. Srbljic for their advic...

Cache coherence problem is pervasive, and a solution to this problem affects the memory performance, influences the amount of...