Abstract — To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDmin of FFs is higher than the optimum supply voltage. In HVFF, the VDD of combinational logic gates is reduced below the VDDmin of FFs while keeping the VDD of FFs at their VDDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage. Index Terms — Minimum operating voltage, subthreshold circuits, variations.

Scaling power supply voltages (VDD’s) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reduc-tions. Circuit delays in the ultra-low voltage region, however, are extremely sen-sitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing mar-gins reduce the energy efficiency benefits of lower VDD, adaptive VDD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive VDD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is pro-posed. In conventional adaptive VDD control systems [1], a critical-path replica is used for the PWM controller of a Buck converter to control VDD. In ultra-low voltage logic circuit design, however, the replica approach is not effective, because the delay mismatch between the actual data path and the critical-path replica is large due to within-die random delay variations. To address such problems, this paper