We address the problem of formally verifying arithmetic instructions of microprocessors implemented by microprograms that contain loops. We try to avoid theorem proving techniques using a new symbolic representation: Binary Moment Diagrams (*BMDs). In order to use *BMDs for verifying sequential circuits as well as microprograms, we extend this representation and define several bit-vector level operators. This extension is then integrated into an automatic verification system. We illustrate the paper with examples and we discuss power and weakness of *BMDs.

. We propose an object-oriented approach for the formal verification of processors. This approach has been validated on significant applications. It is based on a class hierarchy that provides the basic components to describe processors at any abstraction level, and to specify verifications to execute. The originality of our method is to combine an object-oriented model (to ensure genericity) and a computer algebra verification system (to ensure efficiency). Computer experiments with our framework clearly shown three main advantages: processor descriptions are very easy to write down, the core of the verification system is generic so it may be applied without any modification to different processors, and last, the proof times are very short compared with previous approaches. 1 Introduction In this section, we first provide general motivations for hardware verification, and then outline our approach in general terms. 1.1 Motivations In order to produce correct circuits, s...

We propose a framework for the specification and formal verification of processors, based on generic interpreters. The originality of our method is to combine a generic specification environment and an efficient verification system. Computer experiments with our framework have clearly shown three main advantages: processor descriptions are concise and very easy to write down, the core of the verification system is generic so it may be applied without any modification to different processors, and last, the proof times are very short compared with previous approaches. Keywords: Automatic verification of hardware descriptions, very high level specification techniques and tools, formal systems for reasoning about hardware. 1 Introduction 1.1 Motivations In order to produce correct circuits, attention has been paid these last ten years on formal verification methods (for a survey and further justifications see [12]). Formally verifying a circuit consists in proving that its specif...

Several hardware compilers on the market convert from so-called RT level VHDL subsets to logic level descriptions. Such models still need clock signals and the notion of physical time in order to be executable. In a stage of a top-down design starting from the algorithmic level, register transfers are considered, where the timing is not controlled by clock signals and where physical time is not yet relevant. We propose an executable VHDL subset for such register transfer models.