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12
Design Error Diagnosis and Correction via Test Vector Simulation
 IEEE TRANS. CAD
, 1999
"... With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulationbased approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erro ..."
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Cited by 51 (20 self)
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With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulationbased approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits.
Finding and fixing faults
 Paul (Eds.), 13th Conference on Correct Hardware Design and Verification Methods (CHARME ’05
, 2005
"... Knowing that a program has a bug is good, knowing its location is better, but a fix is best. We present a method to automatically locate and correct faults in a finite state system, either at the gate level or at the source level. We assume that the specification is given in Linear Temporal Logic, a ..."
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Cited by 44 (7 self)
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Knowing that a program has a bug is good, knowing its location is better, but a fix is best. We present a method to automatically locate and correct faults in a finite state system, either at the gate level or at the source level. We assume that the specification is given in Linear Temporal Logic, and state the correction problem as a game, in which the protagonist selects a faulty component and suggests alternative behavior. The basic approach is complete but as complex as synthesis. It also suffers from problems of readability: the correction may add state and logic to the system. We present two heuristics. The first avoids the doubly exponential blowup associated with synthesis by using nondeterministic automata. The second heuristic finds a memoryless strategy, which we show is an NPcomplete problem. A memoryless strategy corresponds to a simple, local correction that does not add any state. The drawback of the two heuristics is that they are not complete unless the specification is an invariant. Our approach is general: the user can define what constitutes a component, and the suggested correction can be an arbitrary combinational function of the current state and the inputs. We show experimental results supporting the applicability of our approach.
A Method for Automatic Design Error Location and Correction in Combinational Logic Circuits
 Journal of Electronic Testing: Theory and Applications
, 1996
"... . We present a new diagnostic algorithm, based on backwardpropagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosisoriented test patterns are generated in order to rapidly reduc ..."
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Cited by 14 (4 self)
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. We present a new diagnostic algorithm, based on backwardpropagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosisoriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size. Keywords: design correctness, design debugging, design error diagnosis 1. Introduction As the design of digital systems is becoming increasingly complex, an undetected design error in the late phas...
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
, 1998
"... With the increase of circuit size and complexity, logic design errors can occur. Logic design errors are functional mismatches between the specification and gatelevel implementation. Once a verification tool has found that the design is erroneous, logic debugging must be performed. The research pre ..."
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Cited by 10 (2 self)
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With the increase of circuit size and complexity, logic design errors can occur. Logic design errors are functional mismatches between the specification and gatelevel implementation. Once a verification tool has found that the design is erroneous, logic debugging must be performed. The research presented in this thesis provides a methodology for multiple design error diagnosis and correction. To diagnose an erroneous design, two algorithms based on testvector simulation are presented. The first algorithm is exhaustive on the error space as it exhaustively enumerates the set of all possible error lines and returns the lines of this set that a correction can be applied and rectify the design. The proposed approach exhibits good runtime performance when the number of design errors is less than or equal to two. The second diagnosis approach, uses the results of a testvector simulation procedure to build a graph. Different operations on the graph allow us to explore the error space without performing an explicit enumeration of all error candidates. This makes the method runtime and space efficient for designs corrupted with a larger number of errors. To correct the design, we propose two techniques, one based on testvector simulation, and one
FaultSimulation Based Design Error Diagnosis for Sequential Circuits
 in Proc. ACM/IEEE Design Automation Conf
, 1998
"... This paper addresses the problem of locating design errors in a sequential circuit. For singleerror circuits, we consider a signal f as a potential error source only if the circuit can be completely rectified by resynthesizing f (i.e., changing the function of signal f). In order to handle larger ..."
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Cited by 9 (1 self)
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This paper addresses the problem of locating design errors in a sequential circuit. For singleerror circuits, we consider a signal f as a potential error source only if the circuit can be completely rectified by resynthesizing f (i.e., changing the function of signal f). In order to handle larger circuits, we do not rely on Binary Decision Diagram. Instead, we search for potential error sources by a modified sequential fault simulation process. The main contributions of this paper are twofold: (1) we derive the necessary and sufficient condition of whether an erroneous input sequence (i.e., an input sequence producing erroneous responses) can be corrected by changing the function of a particular internal signal; and (2) we propose a modified fault simulation procedure to check this condition. Our approach does not rely on any error model, and thus, is suitable for general types of errors. Furthermore, it can be easily extended to identify multiple errors. Experimental...
Connection Error Location and Correction in Combinational Circuits
 IN PROC. OF EUROPEAN DESIGN AND TEST CONFERENCE
, 1996
"... We present new diagnostic algorithms for localizing connection errors in combinational circuits. Three types of errors are considered: extra, missing, and bad connection errors. Special test patterns are generated to rapidly locate the error. The algorithms are integrated within the Prevail system. ..."
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Cited by 6 (2 self)
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We present new diagnostic algorithms for localizing connection errors in combinational circuits. Three types of errors are considered: extra, missing, and bad connection errors. Special test patterns are generated to rapidly locate the error. The algorithms are integrated within the Prevail system. Results on benchmarks show that the error is always located, within a time proportional to the product of the circuit size, and the number of used patterns.
Diagnosis is Repair
 In Proc. 16th Int. Workshop on Principles of Diagnosis
, 2005
"... We argue that for sequential circuits, fault localization and repair are one and the same problem. We assume that a specification is given in linear temporal logic and we solve the diagnosis and repair problem for finitestate programs using games. Our approach is sound and it is complete if the spe ..."
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Cited by 5 (2 self)
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We argue that for sequential circuits, fault localization and repair are one and the same problem. We assume that a specification is given in linear temporal logic and we solve the diagnosis and repair problem for finitestate programs using games. Our approach is sound and it is complete if the specification is an invariant. In contrast to known approaches, the repair we find is valid for all possible input sequences, not just for one given test case. We show the applicability of our approach, which has a complexity comparable to that of model checking, on a set of examples. 1
Automatic error correction of tristate circuits
 In Proceedings of the 17th IEEE Internation Conference on Computer Design (ICCD
, 1999
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Automatic Diagnosis may Replace Simulation for Correcting Simple Design Errors
, 2016
"... Automatic diagnosis may replace simulation for correcting simpledesign errors ..."
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Automatic diagnosis may replace simulation for correcting simpledesign errors