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Algorithmic Transforms for Efficient Energy Scalable Computation
, 2000
"... We introduce the notion of energy scalable computation on general purpose processors. The principle idea is to maximize computational quality for a given energy constraint. The desirable energyquality behavior of algorithms is discussed. Subsequently the energyquality scalability of three distinct ..."
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Cited by 30 (6 self)
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We introduce the notion of energy scalable computation on general purpose processors. The principle idea is to maximize computational quality for a given energy constraint. The desirable energyquality behavior of algorithms is discussed. Subsequently the energyquality scalability of three distinct categories of commonly used signal processing algorithms (viz. filtering, frequency domain transforms and classification) are analyzed on the StrongARM SA1100 processor and transformations are described which obtain significant improvements in the energyquality scalability of the algorithm. I. INTRODUCTION In embedded systems, energy is a precious resource and must be used efficiently. Therefore, it is highly desirable that we structure our algorithms and systems in such a fashion that computational accuracy can be traded off with energy requirement. At the heart of such transformations lies the concept of incremental refinement [1]. Consider the scenario where an individual is using his...
PowerAware Systems
, 2000
"... The key to maximizing energy efficiency of systems is understanding and systematically harnessing the tremendous operational diversity they exhibit. We define the powerawareness of a system as its ability to minimize energy consumption by adapting to changes in its operating point. These changes occ ..."
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Cited by 22 (2 self)
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The key to maximizing energy efficiency of systems is understanding and systematically harnessing the tremendous operational diversity they exhibit. We define the powerawareness of a system as its ability to minimize energy consumption by adapting to changes in its operating point. These changes occur as a result of variations in input statistics, desired output quality, tolerable latency and throughput. The key objective of this paper is to unambiguously define the notion of powerawareness, distinguish it from the better understood concept of lowpower, to propose a systematic methodology that enhances powerawareness and finally to illustrate the impact of such reengineering. By applying powerawareness formalisms to systems ranging from multipliers to variable voltage processors, we demonstrate increases in energy efficiency of 60%200%. 1. Introduction A system paradigm that has been gathering momentum recently is that of energyscalable or poweraware design [1]. While the ter...
Approximate Computing: An Emerging Paradigm for EnergyEfficient Design
 Proceedings of the 18th IEEE European Test Symposium
, 2013
"... Abstract — Approximate computing has recently emerged as a promising approach to energyefficient design of digital systems. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result. By relaxing the need for fu ..."
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Cited by 20 (10 self)
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Abstract — Approximate computing has recently emerged as a promising approach to energyefficient design of digital systems. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result. By relaxing the need for fully precise or completely deterministic operations, approximate computing techniques allow substantially improved energy efficiency. This paper reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithmlevel techniques for approximate computing. Keywords—approximate computing, probabilistic computing, stochastic computation, adder, multiplier, lowenergy design I. IMPRECISION TOLERANCE AND ENERGY REDUCTION Energyefficiency has become the paramount concern in
Energy Scalable System Design
, 2002
"... We introduce the notion of energyscalable systemdesign. The principal idea is to maximize computational quality for a given energy constraint at all levels of the system hierarchy. The desirable energyquality (EQ) characteristics of systems are discussed. EQ behavior of algorithms is considere ..."
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Cited by 18 (2 self)
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We introduce the notion of energyscalable systemdesign. The principal idea is to maximize computational quality for a given energy constraint at all levels of the system hierarchy. The desirable energyquality (EQ) characteristics of systems are discussed. EQ behavior of algorithms is considered and transforms that significantly improve scalability are analyzed using three distinct categories of commonly used signalprocessing algorithms on the StrongARM SA1100 processor as examples (viz., filtering, frequency domain transforms and classification). Scalability hooks in hardware are analyzed using similar examples on the Pentium III processor and a scalable programming methodology is proposed. Design techniques for true energy scalable hardware are also demonstrated using filtering as an example.
Modeling and Synthesis of QualityEnergy Optimal Approximate Adders
"... Recent interest in approximate computation is driven by its potential to achieve large energy savings. This paper formally demonstrates an optimal way to reduce energy via voltage overscaling at the cost of errors due to timing starvation in addition. We identify a fundamental tradeoff between err ..."
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Cited by 9 (2 self)
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Recent interest in approximate computation is driven by its potential to achieve large energy savings. This paper formally demonstrates an optimal way to reduce energy via voltage overscaling at the cost of errors due to timing starvation in addition. We identify a fundamental tradeoff between error frequency and error magnitude in a timingstarved adder. We introduce a formal model to prove that for signal processing applications using a quadratic signaltonoise ratio error measure, reducing bitwise error frequency is suboptimal. Instead, energyoptimal approximate addition requires limiting maximum error magnitude. Intriguingly, due to possible error patterns, this is achieved by reducing carry chains significantly below what is allowed by the timing budget for a large fraction of sum bits, using an aligned, fixed internalcarry structure for higher significance bits. We further demonstrate that remaining approximation error is reduced by realization of conditional bounding (CB) logic for lower significance bits. A key contribution is the formalization of an approximate CB logic synthesis problem that produces a rich space of Paretooptimal adders with a range of qualityenergy tradeoffs. We show how CB logic can be customized to result in overand underestimating approximate adders, and how a dithering adder that mixes them produces zerocentered error distributions, and, in accumulation, a reducedvariance error. We demonstrate synthesized approximate adders with energy up to 60 % smaller than that of a conventional timingstarved adder, where a 30% reduction is due to the superior synthesis of inexact CB logic. When used in a larger system implementing an imageprocessing algorithm, energy savings of 40 % are possible. 1.
Controlled timingerror acceptance for low energy idct design
, 2011
"... Abstract — In embedded digital signal processing (DSP) systems, quality is set by a signaltonoise ratio (SNR) floor. Conventional digital design strategies guarantee timing correctness of all operations, which leaves large quality margins in practical systems and sacrifices energy efficiency. This ..."
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Cited by 7 (6 self)
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Abstract — In embedded digital signal processing (DSP) systems, quality is set by a signaltonoise ratio (SNR) floor. Conventional digital design strategies guarantee timing correctness of all operations, which leaves large quality margins in practical systems and sacrifices energy efficiency. This paper presents techniques to significantly improve energy efficiency by shaping the qualityenergy tradeoff achievable via VDD scaling. In an unoptimized design, such scaling leads to rapid loss of quality due to the onset of timing errors. We introduce techniques that modify the behavior of the early and worst timing error offenders to allow for larger VDD reduction. We demonstrate the effectiveness of the proposed techniques on a 2DIDCT design. The design was synthesized using a 45nm standard cell library. The experiments show that up to 45 % energy savings can be achieved at a cost of 10dB peak signaltonoise ratio (PSNR). The resulting PSNR remains above 30dB, which is a commonly accepted value for lossy image and video compression. Achieving such energy savings by direct VDD scaling without the proposed transformations results in a 35dB PSNR loss. The overhead for the needed control logic is less than 3 % of the original design. I.
A lowpower digital filter ic via soft dsp
 In Proceedings of Custom Integrated Circuits Conference
, 1991
"... Abstract In this paper we present an integrated circuit implementation of a soft DSP based lowpower digital filter in 0.35pm, 3.3V CMOS process. Soft DSP is a lowpower technique that employs voltage overscaling (VOS) and algorithmic noisetolerance (ANT) to push the limits of energyefficiency be ..."
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Cited by 3 (1 self)
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Abstract In this paper we present an integrated circuit implementation of a soft DSP based lowpower digital filter in 0.35pm, 3.3V CMOS process. Soft DSP is a lowpower technique that employs voltage overscaling (VOS) and algorithmic noisetolerance (ANT) to push the limits of energyefficiency beyond that achievable by voltage scaling alone. VOS refers. to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level errorcontrol technique that is employed to restore the algorithmic performance degradation in terms of output signaltonoise ratio ( S N R ) caused by VOS. Measured results indicate 40% 67% reduction in energy dissipation over optimally voltagescaled systems with less than ldb loss in S N R for a wide range of filter bandwidths (0.05fs 0.25fs, where f, is the sampling frequency). Introduction Supply voltage scaling has proved to be an effective technique [l] for designing lowpower systems, in general, and digital signal processing (DSP) and communications systems, in particular. However, a reduction in supply voltage results in an increase in the circuit delay given by
A Survey on Information Processing Technologies in Wireless Sensor Networks
"... Abstract: Wireless sensor network(WSN) is a wireless ad hoc network composed of many smart, battery powered nodes. Information processing technologies are very important for extracting reliable and timely information from WSN. But they are very special in WSN compared to the ordinary information pro ..."
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Cited by 2 (0 self)
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Abstract: Wireless sensor network(WSN) is a wireless ad hoc network composed of many smart, battery powered nodes. Information processing technologies are very important for extracting reliable and timely information from WSN. But they are very special in WSN compared to the ordinary information processing technologies. In this paper, the hot spots of the technologies are introduced including energy aware design of DSP algorithms, space time signal processing algorithms and networked information processing algorithms. Finally, the prospect and several future research directions are discussed.
Design of A PowerScalable Digital LeastMeansSquare Adaptive Filter
, 2000
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