As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be realized using programmable logic cores. These cores are blocks of programmable logic that can be embedded into a fixed-function ASIC or a custom chip. Such cores differ from stand-alone FPGAs in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing characteristics of rectangular programmable logic cores. We quantify the effects of having different x and y channel capacities, and show that the optimum ratio between the x and y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Compared to a simple extension of an existing switch block, our new architecture leads to an 8.7 % improvement in density with little effect on speed. Finally, we show that if the channel widths and switch block are chosen carefully the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6 % and the speed penalty is 1.1%.

As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed after fabrication. This paper outlines ways in which programmable logic cores can simplify SoC design, and describes some of the challenges that must be overcome if the use of programmable logic cores is to become a mainstream design technique. Introduction Recent years have seen impressive improvements in the achievable density of integrated circuits. In order to maintain this rate of improvement, designers need new techniques to handle the increased complexity inherent in these large chips. One such emerging technique is the System-on-a-Chip (SoC) design methodology. In this methodology, pre-designed and pre-verified blocks, often called cores or intellectual property (IP),are obtained from ...

As System-on-a-Chip (SoC) design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other intellectual property (IP) in the SoC design methodology, except that their function can be changed after fabrication. In many cases, non-rectangular programmable logic cores are required, either to better mesh with the other IP cores, or because of I/O constraints. However, most CAD algorithm and programmable logic architecture research targets stand-alone field programmable gate arrays (FPGA's), which are invariably square or rectangular. In this thesis, we enable researchers...

First of all, I would like to express my gratitude to my advisor, Dr. Janusz Starzyk, for his support, patience, encouragement throughout my graduate studies, and his invaluable advice during the whole work with this dissertation. He also has taught me innumerable lessons and insights on the workings of academic research in general. Special thanks to Dr. Frank Van Graas, for his financial support of my graduate study, his inspiring and encouraging way to guide me to a deeper understanding of GPS research. I would like to thank the rest of my dissertation committee: Dr. Chris G. Bartone offered much-appreciated advice to start this dissertation research work. Dr. Robert Curtis helped me on electronics when I worked on interfacing FPGA with other hardware. Dr. Surender Jain spent his valuable time to attend my presentation, read my dissertation draft, and gave valuable comments. I am very grateful to all students in VLSI and software radio research groups. I appreciate all their friendships and their collective encouragement to finish this dissertation. I specially thank Abdulqadir A. Alaqeeli and Sanjeev Gunawardena for