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Layout aware design of mesh based NoC architectures
- in Proceedings of the 4th international conference on Hardware/software codesign and system synthesis. ACM
"... Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contri ..."
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Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates systemlevel floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures
"... Abstract—This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target de-vice. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synt ..."
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Abstract—This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target de-vice. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis ap-proach consisting of the following: 1) core to router mapping and 2) custom topology and route generation. In particular, it presents an optimal technique for core to router mapping [stage 1)] and a factor-2 approximation algorithm for custom topology generation [stage 2)]. The superior quality of the techniques is established by experimentation with benchmark applications and by compar-isons with existing approaches. Index Terms—Application specific integrated circuit (ASIC), approximation methods, design automation, network-on-chip. I.
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique
"... Abstract—The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection ar-chitecture that can support the communication requirements for the SoC with the desired performance. This paper presents a ge-netic algorithm-based automated design techniqu ..."
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Abstract—The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection ar-chitecture that can support the communication requirements for the SoC with the desired performance. This paper presents a ge-netic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communica-tion traces on the interconnection network. The technique oper-ates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimen-tation with benchmark applications and comparisons with existing approaches. Index Terms—Design automation, genetic algorithms, net-work-on-chip (NoC), routing. I.
