. This article focuses on principles for the design of e#cient parallel algorithms for distributed memory computing systems. We describe the general trend in the development of architectural properties and evaluate the state-of-the-art in a number of basic primitives like graph embedding, partitioning, dynamic load distribution, and communication which are used, to some extent, within all parallel applications. We discuss possible directions for future work on the design of universal basic primitives, able to perform e#ciently on a broad range of parallel systems and applications, and we also give certain examples of speci#c applications which demand specialized basic primitives in order to obtain e#cient parallel implementations. Finally,we show that programming frames can o#er a convenientway to encapsulate algorithmic know-how on applications and basic primitives and to o#er this knowledge to nonspecialist users in a very e#ectiveway. 1 Introduction Parallel processi...

. A hardware independent method of programming a massively parallel machine #MPP# can best be supported byawell-designed run-time environment. An important problem in this design is the ability of e#ciently simulating networks di#erent from the hardware topology. We will describe the mapping kernel of the virtual processors library for the commercial run-time system PARIX 3 . This kernel contains description classes for several topologies #so-called virtual topologies# and implementations of respectiveembeddings which map given instances of virtual topologies onto others or onto the hardware. Using these functions, PARIX is able to establish concrete virtual topologies with corresponding communication channels. The implemented functions were selected with respect to the well-known criteria for graph embeddings: equal load and small dilation. Additionally,we focus on fast distributed computation and universal applicability. As an example, we will show new methods for e#ciently embedd...

Reconfigurable communication networks for massively parallel multiprocessor systems offer the possibility to realize a number of application demands like special communication patterns or real-time requirements. This paper presents the design principle of a reconfigurable network which is able to realize any graph of maximal degree four. The architecture is based on a special multistage Clos network, constructed out of a number of static routing switches of equal size. Upper bounds on the cut size of 4-regular graphs, if split into a number of clusters, allow minimizing the number of switches and connections while still offering the desired reconfiguration capabilities as well as large scalability and flexible multiuser access. Efficient algorithms configuring the architecture are based on an old result by Petersen 27 about the decomposition of regular graphs. The concept presented here is the basis for the Parsytec SC series of reconfigurable MPP-systems. The currently largest reali...

An important problem in the design of run-time environments for massively parallel systems (MPP) is the ability of efficiently simulating networks different from the hardware topology which leads to a hardware independent kind of programming. We will describe the mapping kernel of the virtual processor library for the commercial run-time system PARIX as well as aspects of this environment. The mapping kernel contains description classes for several topologies (so-called virtual topologies) and implementations of respectiveembeddings which map given instances of virtual topologies onto others or onto the hardware interconnection network of a parallel machine. Using these functions, PARIX can establish concrete virtual topologies with corresponding communication channels. The implemented functions were selected w.r.t. well-known criteria for graph embeddings: fast distributedcomputation, universal applicability, equal load, and small dilation.

. A hardware independent method of programming a massively parallel machine (MPP) can best be supported by a well-designed run-time environment. An important problem in this design is the ability of efficiently simulating networks different from the hardware topology. We will describe the mapping kernel of the virtual processors library for the commercial run-time system PARIX 3 . This kernel contains description classes for several topologies (so-called virtual topologies) and implementations of respective embeddings which map given instances of virtual topologies onto others or onto the hardware. Using these functions, PARIX is able to establish concrete virtual topologies with corresponding communication channels. The implemented functions were selected with respect to the well-known criteria for graph embeddings: equal load and small dilation. Additionally, we focus on fast distributed computation and universal applicability. As an example, we will show new methods for efficient...

this paper we focus on the performance of one of the core numerical algorithms for solving systems of partial di#erencial equations. The algorithm is described in suchaway that it is applicable as a benchmark program and also executable on small machines #e.g. restriction to two-dimensional domains#. The program is ported to the PowerPC 601 based parallel systems GC#PP and PowerXplorer and the GCel#1024 Transputer system. Here, we consider the Poisson problem with Dirichletboundary condition of the form