Abstract—The complexity of two-level logic minimization is a topic of interest to both computer-aided design (CAD) specialists and computer science theoreticians. In the logic synthesis community, two-level logic minimization forms the foundation for more complex optimization procedures that have significant real-world impact. At the same time, the computational complexity of two-level logic minimization has posed challenges since the beginning of the field in the 1960s; indeed, some central questions have been resolved only within the last few years, and others remain open. This recent activity has classified some logic optimization problems of high practical relevance, such as finding the minimal sum-of-products (SOP) form and maximal term expansion and reduction. This paper surveys progress in the field with self-contained expositions of fundamental early results, an account of the recent advances, and some new classifications. It includes an introduction to the relevant concepts and terminology from computational complexity, as well a discussion of the major remaining open problems in the complexity of logic minimization. Index Terms—Computational complexity, logic design, logic minimization, two-level logic. I.

Asynchronous design has been the focus of renewed interest. However, a key bottleneck is the lack of high-quality CAD tools for the synthesis of large-scale systems which also allow design-space exploration. This paper proposes a new synthesis method to address this issue, based on transformations.

While ultra-deep-submicron design presents increasingly difficult challenges for standard synchronous design practices, recent research in asynchronous design techniques is making asynchronous circuits an increasingly practical alternative. These challenges include the increasing pressure for low-power, the growing challenge of predicting increasing impact of wire load and delay, and the performance penalty associated with supporting communication between different clock domains. This paper reviews the different solutions to these problems that the spectrum of existing asynchronous design techniques support. It focuses on techniques for fine-grain twodimensional pipelining that yield ultra-high-speed at nominal power supplies and very low-energy at reduced power supplies.

This paper presents a new approach to two-level hazardfree logic minimization in the context of extended burst-mode finite state machine synthesis targeting generalized C-elements (gC). No currently available minimizers for literal-exact two-level hazard-free logic minimization of extended burst-mode gC controllers can handle large circuits without synthesis times ranging up over thousands of seconds. Even existing heuristic approaches take too much time when iterative exploration over a large design space is required and do not yield minimum results. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms, an approach that has not been considered for minimization of extended burst-mode finite state machines previously. Our algorithm achieves very fast logic minimization by introducing compacted state graphs and cover tables and an efficient singlecube cover algorithm for single-output minimization. Our exact logic minimizer finds minimal number of literal solutions to all currently available benchmarks, in less than one second on a 333 MHz microprocessor — more than three orders of magnitude faster than existing literal exact methods, and over an order of magnitude faster than existing heuristic methods for the largest benchmarks. This includes a benchmark that has never been possible to solve exactly in number of literals before. 1

This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-free logic minimization can handle large circuits without synthesis times ranging up over thousands of seconds. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms. Our algorithm achieves fast logic minimization by using compacted state graphs and cover tables and an efficient algorithm for single-output minimization. Our exact two-level hazard-free logic minimizer finds minimal number of literal solutions and is significantly faster than existing literal exact methods — over two orders of magnitude faster for the largest extended burst-mode benchmarks to date. This includes a benchmark that has never been possible to solve exactly in number of literals before. 1

This paper introduces a new method which, given an arbitrary Boolean function and specified set of (function hazardfree) input transitions, determines if any hazard-free multilevel logic implementation exists. The algorithm is based on iterative decomposition, using disjunction and inversion. Earlier approaches by Nowick/Dill [7] and Theobald/Nowick [8] have been proposed to determine if a hazard-free two-level logic implementation exists. However, it is well-known that the effects of multi-level transformations are quite complex: since they can both decrease and increase logic hazards in a given circuit. In this paper, a method is proposed to solve the hazard-free multi-level existence problem. The method is proven to be both sound and complete for a large class of multi-level implementations. A novel contribution is to show that, if any hazard-free multi-level solution exists, then a hazard-free solution always exists using only 3 logic levels, in a 3-level NAND or OR-AND-OR structure. Moreover, in this case, it is shown there always exists a unique canonical hazard-free 3-level implementation.