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...pplied directly to the quantiser input, and thus affect its growth rate. Interestingly, the number of limit cycle periods before break-up occurs hardly differs between feedback and feedforward designs=-=[12, 13]-=-. Apparently, even though the dynamics of a feedback SDM appear to be different from that of a feedforward design, the results are virtually identical. Results are not presented here for designs with ...

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...limit cycles are highly dependent onsinitial conditions. Contrary to linear filter design theory,scareful placement of poles and zeros in SDM designsdoes not typically result in limit cycle avoidance =-=[9]-=-.sDithering [6] and other methods, like bit flippingsmethods [10] or the more efficient mechanism describedsin [11], have proven to be effective in removing limitscycles. This section is concerned wit...

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...to reduce power consumption and design complexity [1], limit cycles are generally unwanted since they result in frequency components in the output bitstream which were not present in the input signal =-=[2]-=-. Digital filters may be designed so as to minimize the occurrence of limit cycles [3], but it is not yet clear if this approach may be extended to limit cycles in SDMs. In practice, limit cycle preve...

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... The requirements that thesADC has to fulfill are set by both the standard characteristicssand the receiver architecture.s2. Sigma delta modulator architecturesThe sigma delta conversion technique [1]=-=[2]-=-[6] has beensin existence for many years, but recent technologicalsadvances now make the devices practical and their use issbecoming widespread. The converters have found homes inssuch applications as...

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...e same sequence length as a first-order EFM (EFM1) in an MM-MASH. In addition, the method that is required to setup the quantisation moduli of the MM-MASH is introduced. The theory is validated by simulation. I. INTRODUCTION Digital delta-sigma modulators (DDSM) are widely used in consumer electronic equipment such as cellular telephones, MP3 players and wireless-LANs. A DDSM is composed of several error feedback machines (EFM). The architectures of EFMs decide the sequence length of DDSMs. Since a short sequence length results in unwanted frequency components in the output frequency spectrum [1], much research has been done into maximising the sequence length. There are two approaches to lengthen the sequence length: stochastic and deterministic methods. The most common stochastic approach is that of dithering [2] [3]. However, it requires extra hardware and inherently introduces additional noise in the the useful frequency band. Thus, some deterministic design methodologies have been proposed to maximise the sequence length. Borkowski [4] sets the initial condition of the registers to make the sequence length of the conventional MASH DDSM reach its maximum value. Hosseini [5] modifi...

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...istortion increases. Because of this, for data processing applications it is very important to predict and describe possible limit cycles. Since the pioneering work of Gray and his co-workers beginning with [3], a number of researchers have contributed to the development of a theory of Σ∆ modulation. Main results concerning the limit cycles for low order Σ∆ modulators are presented in [4], [5], [6]. In [7] a procedure for characterizing and validating potential limit cycles is presented. This enables to carry out an exhaustive search for cyclic sequences up to a length of 40 clock periods. In [8], [9] authors use state space approach and present a mathematical framework for the description of limit cycles in 1-bit Σ∆ modulators for constant inputs. Here we present a method for description and validation of potential limit cycles for high order modulators. Especially we focus our attention on constant input signals. The method is based on the decomposition of the general N-th order modulator presented in [10], [11], [12]. Using this presentation the modulator could be considered as made up of N first order modulators (generally complex modulators), which interact only through the quant...

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...systems and third-generation (3-G) cellular technology. Limit cycles (defined as a sequence of L output bits which repeats itself indefinitely) are one of the most common sources of instabilities [2]-=-=[4]-=-. Also, in synchronous code division multiple access communication systems, limit cycles have been pointed out as the dominant source of performance degradation [5]. For the above reasons, new procedu...

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...nge. The requirements that the ADC has to fulfill are set by both the standard characteristics and the receiver architecture. Sigma delta modulator architecture The sigma delta conversion technique[1]=-=[2]-=-[6] has been in existencefor many years, but recent technological advances now makethe devices practical and their use is becoming widespread.The converters have found homes in such applications ascom...