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38
Optimal Reconfiguration Sequence Management
- in Asia South Pacific Design Automation Conference (ASPDAC
, 2003
"... In this paper, we present an efficient optimal algorithm for minimizing runtime reconfiguration (context switching) delay of executing an application on a reconfigurable system. We assume that the basic operations of the application are already scheduled and each of them has to be realized on the re ..."
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In this paper, we present an efficient optimal algorithm for minimizing runtime reconfiguration (context switching) delay of executing an application on a reconfigurable system. We assume that the basic operations of the application are already scheduled and each of them has to be realized on the reconfigurable fabric in order to be executed. The modeling and algorithm are both applicable to partially reconfigurable platforms as well as MultiFPGA systems. The algorithm can be directly applied to minimize the application runtime for many typical classes of applications, where the actual execution delay of basic operations is negligible compared to reconfiguration delay. We prove the optimality and efficiency of our algorithm and report experimental results, which demonstrate 40% to 2.5% improvement in total runtime reconfiguration delay.
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems
- PROCEEDINGS OF IEEE WORKSHOP ON RAPID SYSTEM PROTOTYPING
, 2000
"... The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are still many challenging problems to be solved before any practical general-purpose reconfigurable system is built. One fundame ..."
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The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are still many challenging problems to be solved before any practical general-purpose reconfigurable system is built. One fundamental problem is the placement of the modules on the reconfigurable functional unit (RFU). In reconfigurable systems, we are interested both in online placement, where arrival time of tasks is determined at runtime and is not known a priori, and offline in which the schedule is known at compile time. In the case of offline placement, we are willing to spend more time during compile time to find a compact floorplan for the RFU modules and utilize the RFU area more efficiently. In this paper we present offline placement algorithms based on simulated annealing and greedy methods and show the superiority of their placements over the ones generated by an online algorithm.
The Proteus Processor — A Conventional CPU with Reconfigurable Functionality
- In 9th International Workshop on Field Programmable Logic and Applications
, 1999
"... Abstract. This paper describes the starting position for research beginning at ..."
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Abstract. This paper describes the starting position for research beginning at
Architecture-Independent Design for Run-Time Reconfigurable Custom Computing Machines
, 2000
"... The configurable computing research community has provided a wealth of evidence that computational platforms based on FPGA technology are capable of cost-effectively accelerating certain kinds of computations. One actively growing area in the research community examines the benefits to computation t ..."
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The configurable computing research community has provided a wealth of evidence that computational platforms based on FPGA technology are capable of cost-effectively accelerating certain kinds of computations. One actively growing area in the research community examines the benefits to computation that can be gained by reconfiguring the FPGAs in a system during the execution of an application. This technique is commonly referred to as run-time reconfiguration. Widespread acceptance of run-time reconfigurable custom computing depends upon the existence of high-level automated design tools. Given the wide variety of available platforms and the rate that the technology is evolving, a set of architecturally independent tools that provide the ability to port applications between different architectures will allow applicationbased intellectual property to be easily migrated between platforms. A Java implementation of such a toolset, called Janus, is presented and analyzed here. In this environment, developers create a Java class that describes the structural behavior of an application. The design framework allows hardware and software modules to be freely intermixed. During the compilation phase of the development process, the Janus tools analyze the structure of the application and adapt it to the target architecture. Janus is capable of structuring the run-time behavior of an application to take advantage of the resources available on the platform. Examples of applications developed using the toolset are presented. The performance of the applications is reported. The retargeting of applications for multiple hardware architectures is demonstrated.
Java Debug Hardware Models using JBits
, 2001
"... This paper presents a methodology for extending FPGA bitstreamlevel debug and simulation capabilities, through the inclusion of Java/JBits-based hardware device models. Using the JBits API, behavioral hardware models can be written in Java and used in simulations with the Virtex Device Simulat ..."
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This paper presents a methodology for extending FPGA bitstreamlevel debug and simulation capabilities, through the inclusion of Java/JBits-based hardware device models. Using the JBits API, behavioral hardware models can be written in Java and used in simulations with the Virtex Device Simulator. Java lends the advantages typically associated with object-oriented design languages to FPGA bitstream-level debugging and simulation. This leads to more efficient design of hardware models as well as more flexibility in testing. Java also provides unique capabilities that assist interaction with the Java Debug Hardware Models (JDHM) during simulation. Also, the advantages of bitstream level design control and run-time reconfiguration capabilities provided by JBits offers benefits over traditional simulation techniques.
Methods for Securing the Integrity of FPGA Configurations
, 2006
"... As Field Programmable Gate Arrays (FPGAs) continue to become integral parts of embedded systems, it is imperative to consider their security. While much of the research in this field is oriented toward the protection of the intellectual property contained in the FPGA’s configuration, the protection ..."
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As Field Programmable Gate Arrays (FPGAs) continue to become integral parts of embedded systems, it is imperative to consider their security. While much of the research in this field is oriented toward the protection of the intellectual property contained in the FPGA’s configuration, the protection of the design’s integrity from malicious attack against the con-figuration is critical to the operation of the system. Methods for attacking the configuration are semi-invasive attacks, such as fault injection, and data tampering of incoming partial bitstreams. This thesis introduces methods for securing the integrity of an FPGA’s configuration. The design and implementation is discussed for a system that consists of three parts. The first subsystem monitors the running configuration. The second subsystem authenticates partial bistreams that may be used for repairing the configuration from malicious alterations during run-time. The third subsystem indicates if the system itself succumbs to a malicious attack. The system is implemented on-chip, allowing the FPGA to effectively secure itself from attack.
Formally Analysed Dynamic Synthesis of Hardware
- in Theorem Proving in Higher Order Logics: Emerging Trends: 11th International Conference (TPHOLs'98
, 2001
"... . Dynamic hardware reconfiguration based on run-time system specialization is viable with Xilinx XC6200 series FPGAs. The research challenge for formal verification is to help ensure the correctness of dynamically generated hardware. In this paper, the approach is to verify a specialization synthesi ..."
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. Dynamic hardware reconfiguration based on run-time system specialization is viable with Xilinx XC6200 series FPGAs. The research challenge for formal verification is to help ensure the correctness of dynamically generated hardware. In this paper, the approach is to verify a specialization synthesis algorithm used to reconfigure FPGA designs. The verification approach is based on a deep embedding of a language for netlists and the relational hardware modeling style. 1 Introduction Most micro-electronic circuit design is done as ASIC design. The design is validated extensively, either by simulation or by formal verification methods, before it is manufactured. The production of the design as a chip will take several months before the designer can test the hardware itself. If the system fails to satisfy the functional specification at the testing stage, the designers must redesign the circuit and redo the whole validation, production, and test cycle. The flexibility of implementing a ...
Reconfigurable Computing and Active Networks
- ERSA ’03, Las Vegas, NV
"... This paper describes an experimental platform, optimised for Active Network processing. The system is based on a PC running Linux and operating as a router. The active applications are downloaded in a FPGA based PCI board. An embedded hardware module monitors and manages the active applications at r ..."
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This paper describes an experimental platform, optimised for Active Network processing. The system is based on a PC running Linux and operating as a router. The active applications are downloaded in a FPGA based PCI board. An embedded hardware module monitors and manages the active applications at run time. A stable and safe reconfigurable platform for the Active Applications is the objective of this investigation.
Implementation of a Runtime Environment for Reconfigurable Hardware Operating Systems
- Swiss Federal Institute of Technology Zurich (ETH) Computer Engineering and Networks Laboratory, TIK Report Nr. 195
, 2004
"... We present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex. To that end, the FPGA’s reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks. A bus-based communication infrastr ..."
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We present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex. To that end, the FPGA’s reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks. A bus-based communication infrastructure allows for task communication and I/O. We discuss the design of the runtime system and its prototype implementation on an reconfigurable board architecture that was specifically tailored to reconfigurable hardware operating system research.
