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527
Nanowirebased programmable architectures
 ACM Journal on Emerging Technologies in Computing Systems
, 2005
"... Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively fieldeffect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems ..."
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Cited by 59 (6 self)
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Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively fieldeffect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottomup synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowirebased architectures which can bridge between lithographic and atomicscale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowirebased programmable architectures offer one to two orders of magnitude greater mappedlogic density than defectfree lithographic FPGAs at 22nm.
An algorithm for bidecomposition of logic functions
 Proc. DAC '01
, 2001
"... We propose a new BDDbased method for decomposition of multioutput incompletely specified logic functions into netlists of twoinput logic gates. The algorithm uses the internal don’tcares during the decomposition to produce compact wellbalanced netlists with short delay. The resulting netlists a ..."
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Cited by 53 (19 self)
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We propose a new BDDbased method for decomposition of multioutput incompletely specified logic functions into netlists of twoinput logic gates. The algorithm uses the internal don’tcares during the decomposition to produce compact wellbalanced netlists with short delay. The resulting netlists are provably nonredundant and facilitate test pattern generation. Experimental results over MCNC benchmarks show that our approach outperforms SIS and other BDDbased decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time. 1.
ABC: An Academic IndustrialStrength Verification Tool
"... Abstract. ABC is a publicdomain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on AndInverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of ..."
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Cited by 52 (14 self)
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Abstract. ABC is a publicdomain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on AndInverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.
A performance study of BDDbased model checking
 IN PROCEEDINGS OF THE FORMAL METHODS ON COMPUTERAIDED DESIGN
, 1998
"... We present a study of the computational aspects of model checking based on binary decision diagrams (BDDs). By using a tracebased evaluation framework, we are able to generate realistic benchmarks and perform this evaluation collaboratively across several different BDD packages. This collaboration ..."
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Cited by 50 (5 self)
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We present a study of the computational aspects of model checking based on binary decision diagrams (BDDs). By using a tracebased evaluation framework, we are able to generate realistic benchmarks and perform this evaluation collaboratively across several different BDD packages. This collaboration has resulted in significant performance improvements and in the discovery of several interesting characteristics of model checking computations. One of the main conclusions of this work is that the BDD computations in model checking and in building BDDs for the outputs of combinational circuits have fundamentally different performance characteristics. The systematic evaluation has also uncovered several open issues that suggest new research directions. We hope that the evaluation methodology used in this study will help lay the foundation for future evaluation of BDDbased algorithms.
FRAIGs: A unifying representation for logic synthesis and verification
, 2005
"... ANDINV graphs (AIGs) are Boolean networks composed of twoinput ANDgates and inverters. In the known applications, such as equivalence checking and technology mapping, AIGs are used to represent and manipulate Boolean functions. AIGs powered by simulation and Boolean satisfiability lead to function ..."
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Cited by 48 (13 self)
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ANDINV graphs (AIGs) are Boolean networks composed of twoinput ANDgates and inverters. In the known applications, such as equivalence checking and technology mapping, AIGs are used to represent and manipulate Boolean functions. AIGs powered by simulation and Boolean satisfiability lead to functionally reduced AIGs (FRAIGs), which are “semicanonical ” in the sense that each FRAIG node has unique functionality among all the nodes currently present in the FRAIG. The paper shows that FRAIGs can be used to unify and enhance many phases of logic synthesis: from the representation of the original and the intermediate netlists derived by logic optimization, through technology mapping over multiple logic structures, to combinational equivalence checking. Experimental results on large public benchmarks confirm the practicality of using FRAIGs throughout the logic synthesis flow. 1
ComputerAided Synthesis And Verification Of GateLevel Timed Circuits
, 1995
"... In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirement ..."
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Cited by 47 (21 self)
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In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirements. Traditional academic asynchronous designs methods use unbounded delay assumptions, resulting in circuits that are verifiable, but ignore timing for simplicity, leading to unnecessarily conservative designs. In industry, however, timing is critical to reduce both chip area and circuit delay. Due to a lack of formal methods that handle timing information correctly, circuits with timing constraints usually require extensive simulation to gain confidence in the design. This thesis bridges this gap by introducing timed circuits in which explicit timing information is incorporated into the specification and utilized throughout the design procedure to optimize the implementation. Our timed circu...
NanowireBased Sublithographic Programmable Logic Arrays
, 2004
"... How can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottomup material synthesis techniques to build PLAs using molecularscale nanowires. Our new designs accommodate technologie ..."
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Cited by 47 (6 self)
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How can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottomup material synthesis techniques to build PLAs using molecularscale nanowires. Our new designs accommodate technologies where the only postfabrication programmable element is a nonrestoring diode. We introduce stochastic techniques which allow us to restore the diode logic at the nanoscale so that it can be cascaded and interconnected for general logic evaluation. Under conservative assumptions using 10nm nanowires and 90nm lithographic support, we project yielded logic density around 500,000nm 2 /or term for a 60 orterm array; a complete 60term, twolevel PLA is roughly the same size as a single 4LUT logic block in 22nm lithography. Each or term is comparable in area to a 4transistor hardwired gate at 22nm. Mapping sample datapaths and conventional programmable logic benchmarks, we estimate that each 60orterm PLA plane will provide equivalent logic to 5–10 4input LUTs.
Gatelevel Power Estimation Using Tagged Probabilistic Simulation
"... In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagg ..."
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Cited by 42 (1 self)
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In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the notion of tagged (probability) waveforms, which model the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. From the tagged waveform, one can calculate the switching activity and hence the average power consumption of the circuit node. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 23 improvement in accuracy of power estimates over previous probabilistic simulation approaches.
Active hardware metering for intellectual property protection and security
 in USENIX Security Symposium, 2007
"... Abstract We introduce the first active hardware metering scheme that aims to protect integrated circuits (IC) intellectual property (IP) against piracy and runtime tampering. The novel metering method simultaneously employs inherent unclonable variability in modern manufacturing technology, and fun ..."
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Cited by 42 (21 self)
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Abstract We introduce the first active hardware metering scheme that aims to protect integrated circuits (IC) intellectual property (IP) against piracy and runtime tampering. The novel metering method simultaneously employs inherent unclonable variability in modern manufacturing technology, and functionality preserving alternations of the structural IC specifications. Active metering works by enabling the designers to lock each IC and to remotely disable it. The objectives are realized by adding new states and transitions to the original finite state machine (FSM) to create boosted finite state machines(BFSM) of the pertinent design. A unique and unpredictable ID generated by an IC is utilized to place an BFSM into the powerup state upon activation. The designer, knowing the transition table, is the only one who can generate input sequences required to bring the BFSM into the functional initial (reset) state. To facilitate remote disabling of ICs, black hole states are integrated within the BFSM. We introduce nine types of potential attacks against the proposed active metering method. We further describe a number of countermeasures that must be taken to preserve the security of active metering against the potential attacks. The implementation details of the method with the objectives of being lowoverhead, unclonable, obfuscated, stable, while having a diverse set of keys is presented. The active metering method was implemented, synthesized and mapped on the standard benchmark circuits. Experimental evaluations illustrate that the method has a lowoverhead in terms of power, delay, and area, while it is extremely resilient against the considered attacks.
LowPower FPGA Using Predefined DualVdd/DualVt Fabrics
 FPGA'04
, 2004
"... Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use predefined dualVdd and dualVt fabrics to reduce FPGA power. We design FPGA circuits with dualVdd/dualVt to e#ectively reduce both dynamic power and leakage power, and define dualVdd/dualVt ..."
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Cited by 39 (12 self)
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Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use predefined dualVdd and dualVt fabrics to reduce FPGA power. We design FPGA circuits with dualVdd/dualVt to e#ectively reduce both dynamic power and leakage power, and define dualVdd/dualVt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including powersensitivity based voltage assignment and simulatedannealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the predefined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the predesigned dualVdd layout pattern introduces nonnegligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dualVdd FPGAs. To our best knowledge, it is the first indepth study on applying both dualVdd and dualVt to FPGA considering circuits, fabrics and CAD algorithms.