We describe a method for reducing the complexity of temporal logic model checking in systems composed of many parallel processes. The goal is to check properties of the components of a system and then deduce global properties from these local properties. The main difficulty with this type of approach is that local properties are often not preserved at the global level. We present a general framework for using additional interface processes to model the environment for a component. These interface processes are typically much simpler than the full environment of the component. By composing a component with its interface processes and then checking properties of this composition, we can guarantee that these properties will be preserved at the global level. We give two example compositional systems based on the logic CTL*.

The paper deals with verification of untimed branching time properties of Time Petri Nets. The atomic variant of the geometric region method for preserving properties of CTL and ACTL is improved. Then, it is shown, for the first time, how to apply the partial order reduction method to deal with next-time free branching properties of Time Petri Nets. The above two results are combined offering an efficient method for model checking of ACTL X and CTL X properties of Time Petri Nets.

Recently, model checking of Petri nets based on partial order semantics w.r.t. temporal logic formulae has been extended to time Petri nets. In this paper, we present an improved algorithm for computing the McMillan-unfolding of a time Petri net which gives a nite representation of the partial order semantics and some experimental results of its implementation within the PEP tool.

Bounded Model Checking (BMC) based on SAT methods consists in searching for a counterexample of a particular length and to generate a propositional formula that is satis able i such a counterexample exists. Our paper shows how the concept of bounded model checking can be extended to deal with TACTL (the universal fragment of TCTL) properties of Timed Automata.

This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.

Conformance has been used as a correctness criterion for asynchronous circuits. In the case of untimed systems, conformance of an implementation to a specication is equivalent to the failurefreeness between the implementation and the mirror of the specication. For bounded-delay systems, in general this property does not hold. In this paper, we dene various notions of failure and examine whether the above propery holds or not. We then discuss alternative eective algorithms for conformance checking of bounded-delay asynchronous circuits. I.

This proposal presents an implementation of trace theoretic verication in timed circuits detailing research in 3 specic areas: correctness, reduction, and interpretation. This research proposes to rst develop a denition of correctness for TEL structures that allows conformance verication of real-time constraints. It proposes to survey the utility of adapting state space reduction methods to TEL structures with POSET timing. Based on the survey, this research proposes to develop a method of state space reduction that is suited to TEL semantics. Finally, this paper proposes work in the interpretation of verication results by providing the user with a sucient set of timing assumptions to guarantee conformance of an implementation to its specication. 1 Introduction To increase performance, circuit designers are beginning to experiment with timed circuits. Timed circuits are a class of circuits that rely on timing information for correct functionality [1, 2, 3, 4]. This is e...