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Generating Synthetic Benchmark Circuits for Evaluating CAD Tools
, 2000
"... For the development and evaluation of CADtools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation too ..."
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Cited by 35 (9 self)
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For the development and evaluation of CADtools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graphbased benchmark generation method to include functional information. The use of a userspecified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timingdriven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timingaware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.
On Synthetic Benchmark Generation Methods
 IN PROC. IEEE INTL. SYMP. ON CIRCUITS AND SYSTEMS
, 2000
"... In the process of designing complex chips and systems, the use of benchmark designs is often necessary. However, the existing benchmark suites are not sufficient for the evaluation of new architectures and EDA tools; synthetic benchmark circuits are a viable alternative. In this paper, a systematic ..."
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Cited by 11 (3 self)
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In the process of designing complex chips and systems, the use of benchmark designs is often necessary. However, the existing benchmark suites are not sufficient for the evaluation of new architectures and EDA tools; synthetic benchmark circuits are a viable alternative. In this paper, a systematic approach for the generation and evaluation of synthetic benchmark circuits is presented. A number of existing benchmark generation methods are examined using direct validation of size and topological parameters. This exposes certain features and drawbacks of the different methods.
Characterization of Feasible Retimings
, 2001
"... We present a theorem which characterizes all feasible retimings for a stronglyconnected graph. For such graphs, we give necessary and sufficient conditions for the achievability of a chosen target retiming. We describe an application which combines floorplanning and retiming which utilizes this cha ..."
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Cited by 7 (1 self)
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We present a theorem which characterizes all feasible retimings for a stronglyconnected graph. For such graphs, we give necessary and sufficient conditions for the achievability of a chosen target retiming. We describe an application which combines floorplanning and retiming which utilizes this characterization. Experimental results show our techniques yield superior clock frequencies with a minor increase in wirelength.
Recent Advances in SystemLevel Interconnect Prediction
 IEEE Circuits and Systems Newsletter
, 2000
"... The exciting, new field of SystemLevel Interconnect Prediction emerged from research of the early 1970's but it took until 1999 before a cohesive research community for interconnect prediction was established. New research results are becoming available and the last couple of years have brou ..."
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Cited by 5 (1 self)
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The exciting, new field of SystemLevel Interconnect Prediction emerged from research of the early 1970's but it took until 1999 before a cohesive research community for interconnect prediction was established. New research results are becoming available and the last couple of years have brought both more interest and more progress in the field than in the thirty years before. This paper is an introduction to the field and provides an overview of some of the recent advances in systemlevel interconnect prediction. 1 Introduction As mainstream processors surpass gigahertz global clock frequencies and new design and process technologies enable even higher performance, much attention is directed toward managing the influence of interconnects in deep submicron designs. Today, interconnects are the limiting factor for both performance and density, i.e., the value and the cost of the VLSI system. Guided by better models of interconnect performance at the atomistic and grain levels of...
Intrinsic Shortest Path Length: A New, Accurate A Priori
"... A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate estimator of net lengths. We observe that in “good ” placements, the length of a net is very strongly correlated with the numbers of nets in the ..."
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Cited by 2 (1 self)
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A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate estimator of net lengths. We observe that in “good ” placements, the length of a net is very strongly correlated with the numbers of nets in the shortest paths connecting node pairs of the net, when each shortest path is computed under the restriction that the net itself does not exist. We refer to this as the net’s intrinsic shortest path length (ISPL). Using ISPL as a wirelength estimator has several advantages: (1) it transparently handles multipin nets and is a strong predictor of their length; (2) it strongly correlates with the average netlist wirelength; (3) it has a distribution that is similar to that of wirelength; and (4) it acts as a good predictor for individual net lengths. Based on ISPLs, we characterize VLSI netlists with a single value and develop an intuitive, empirical link between our proposed value and the Rent parameter. We also analytically model the relationship between ISPL and wirelength, and use ISPLs in two practical applications: a priori total wirelength estimation and a priori global interconnect prediction. 1
New Ways of Generating Large Realistic Benchmarks for Testing Synthesis Tools
 PROC. 9TH INT. WORKSHOP ON BOOLEAN PROBLEMS
, 2010
"... In this paper we propose several methods of generating large benchmark circuits for testing logic synthesis tools. The benchmarks are derived from real circuits, so that they are functionally equivalent to their origins. We introduce misleading and/or redundant structures into them, making the bench ..."
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Cited by 2 (2 self)
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In this paper we propose several methods of generating large benchmark circuits for testing logic synthesis tools. The benchmarks are derived from real circuits, so that they are functionally equivalent to their origins. We introduce misleading and/or redundant structures into them, making the benchmark size blow up significantly, with respect to the original circuit. Such benchmarks can be advantageously used for testing logic synthesis tools; the aim is to discover whether particular synthesis processes are sensitive or immune to particular circuit transformations. 1
ZeroChange Netlist Transformations: A New Technique for Placement Benchmarking
"... In this paper we introduce the concept of zerochange netlist transformations to (1) quantify the suboptimality of existing placers on artificially constructed instances, and (2) “partially ” quantify the suboptimality of placers on synthesized netlists from arbitrary netlists by giving lower bounds ..."
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In this paper we introduce the concept of zerochange netlist transformations to (1) quantify the suboptimality of existing placers on artificially constructed instances, and (2) “partially ” quantify the suboptimality of placers on synthesized netlists from arbitrary netlists by giving lower bounds to the suboptimality gap. Given a netlist and its placement from a placer, we formally define a class of netlist transformations that synthesize a different netlist from the given netlist but yet the new netlist has the same HalfPerimeter Wire Length (HPWL) on the given placement. Furthermore, and more importantly, the optimal HPWL value of the new netlist is no less than that of the original netlist. By applying our transformations and reexecuting the placer, we can interpret any deviation in HPWL as a lower bound to the gap from the optimal HPWL value of the new synthesized netlist. Our transformations allow us to (1) increase the cardinality of hyperedges, (2) reduce the number of hyperedges, and (3) increase the number of twopin edges, while maintaining the placement HPWL constant. We also develop methods that apply zerochange netlist transformations to synthesize netlists having typical netlist statistics. Furthermore, we extend our approach to estimate suboptimality of other metrics such as rectilinear minimumspanning tree (RMST) and minimumSteiner tree. Using these transformations, the suboptimality of some of the existing academic placers (FengShui [35], Capo [4], mPL [10], Dragon