This paper presents a novel system-level performance analysis technique to support the design of custom communication architectures for system-on-chip integrated circuits. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e.g., simulation of the complete system) or are not accurate enough to drive the design of the communication architecture (e.g., techniques that perform a "static" analysis of the system performance). Our technique is based on a hybrid trace-based performance-analysis methodology in which an initial cosimulation of the system is performed with the communication described in an abstract manner (e.g., as events or abstract data transfers). An abstract set of traces are extracted from the initial cosimulation containing necessary and sufficient information about the computations and communications of the system components. The system designer then specifies a communication architecture by: 1) selecting a topology consisting of dedicated as well as shared communication channels (shared buses) interconnected by bridges; 2) mapping the abstract communications to paths in the communication architecture; and 3) customizing the protocol used for each channel. The traces extracted in the initial step are represented as a communication analysis graph (CAG) and an analysis of the CAG provides an estimate of the system performance as well as various statistics about the components and their communication. Experimental results indicate that our performance-analysis technique achieves accuracy comparable to complete system simulation (an average error of 1.88%) while being over two orders of magnitude faster.

Abstract-A system for interpretation of images of paper-based line drawings is described. Since a typical drawing contains both test strings and graphics, an algorithm has been developed to locate and separate text strings of various font size, style, and orientation. This is accom-plished by applying the Hough transform to the centroids of connected components in the image. The graphics in the segmented image is pro-cessed to represent thin entities by their core-lines and thick objects by their boundaries. The core-lines and boundaries are segmented into straight line segments and curved lines. The line segments and their interconnections are analyzed to locate minimum redundancy loops which are adequate to generate a succinct description of the graphics. Such a description includes the location and attributes of simple po-lygonal shapes, circles, and interconnecting lines, and a description of the spatial relationships and occlusions among them. Hatching and fill-ing patterns are also identified. The performance of the system is eval-uated using several test images and the results are presented. The su-periority of these algorithms in generating meaningful interpretations of graphics, compared to conventional data compression schemes, is clear from these results. Index Terns-Document image analysis, drawing conversion, fea-ture extraction, graphics recognition, image understanding, knowl-edge-based systems, line-drawing interpretation, pattern recognition, text segmentation, vectorization. I.

Overheating has been acknowledged as a major problem during the testing of complex system-on-chip (SOC) integrated circuits. Several power-constrained test scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the non-uniform distribution of heat dissipation across the die and the physical adjacency of simultaneously active cores. This paper proposes a new test scheduling approach that is able to produce short test schedules and guarantee thermal-safety at the same time. Two thermal-safe test scheduling algorithms are proposed. The first algorithm computes an exact (shortest) test schedule that is guaranteed to satisfy a given maximum temperature constraint. The second algorithm is a heuristic intended for complex systems with a large number of embedded cores, for which the exact thermal-safe test scheduling algorithm may not be feasible. Based on a low-complexity test session thermal cost model, this algorithm produces near-optimal length test schedules with significantly less computational effort compared to the optimal algorithm. ∗ A preliminary version of this work was presented at the Design Automation and Test in Europe (DATE) Conference in March 2005.

Abstract—Epitaxially grown self-assembled InAs–InGaAs– GaAs quantum dots (QDs) are exploited for the development of large-format long-wavelength infrared focal plane arrays (FPAs). The dot-in-a-well (DWELL) structures were experimentally shown to absorb both 45 and normal incident light, therefore, a reflection grating structure was used to enhance the quantum efficiency. The devices exhibit peak responsivity out to 8.1 m, with peak detectivity reaching 1 10 10 Jones at 77 K. The devices were fabricated into the first long-wavelength 640 512 pixel QD infrared photodetector imaging FPA, which has produced excellent infrared imagery with noise equivalent temperature difference of 40 mK at 60-K operating temperature. Index Terms—Focal plane array, infrared detector, quantum dots (QDs). I.

We present a study on the dynamic stability of the perfectly matched layer (PML) absorbing boundary condition for finite-difference time-domain (FDTD) simulations of electromagnetic radiation and scattering problems in body-conformal orthogonal grids. This work extends a previous dynamic stability analysis of Cartesian, cylindrical and spherical PMLs to the case of a conformal PML. It is shown that the conformal PML defined over surface terminations with positive local radii of curvature (concave surfaces as viewed from inside the computational domain) is dynamically stable, while the conformal PML defined over surface terminations with a negative local radius (convex surfaces as viewed from inside the computational domain) is dynamically unstable. Numerical results illustrate the analysis.

Abstract—The design of efficient time compression support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. The test data outputs in BIST are ultimately compressed by the time compaction hardware, commonly called a response analyzer, into signatures. Several output response compaction techniques to aid in the synthesis of such support circuits already exist in literature, and parity bit signature coupled with exhaustive testing is already well known to have certain very desirable properties in this context. This paper reports new time compaction techniques utilizing the concept of parity bit signature that facilitates implementing such support circuits using nonexhaustive or compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information as best as possible. Recently, Jone and Das proposed a

Abstract—The use of resonant tunneling (RT) barriers in the design of quantum dots-in-a-well (DWELL) infrared photodetectors is reported. The design of RT barriers for a variety of goals has been discussed. For simple DWELL designs, we demonstrate 2–3 orders-of-magnitude reduction in the dark current, with significant increase in the specific detectivity () of the device. Two RT barriers are designed to selectively extract midwave and longwave components of the spectral response. We also report the use of RT barriers on strain-optimized quantum dots-in-a-double-well (DDWELL) structures to achieve very low dark current levels with peak of 2 9 10 10 cm Hz 1 2 /W for a longwave infrared detection. Ability to select a particular wavelength in the spectral response is demonstrated with DDWELL architectures as well. Index Terms—Quantum dots, infrared, resonant tunneling (RT), photodetectors, dots in a well (DWELL). I.