Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs by Luciano Lavagno Doctor of Philosophy in Electrical Engineering and Computer Sciences University of California at Berkeley Professor Alberto Sangiovanni-Vincentelli, Chair The design of asynchronous circuits is increasingly important in solving problems such as complexity management, modularity, power consumption and clock distribution in large digital integrated circuits. The task is difficult mainly for the possible presence of hazards, i.e. deviations from the expected circuit behavior due to gate and wire delays. Efficient synthesis tools, which take into account the need for testing manufactured circuits, are required. The problem has been studied extensively in the past, but no satisfactory automated solution using a realistic delay model has been presented. This thesis introduces the problem through an extensive literature review and then proposes a synthesis procedure based on the...

This paper shows a method to represent a multipleoutput function: Encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n + u) binary variables to represent an n-input m-output function, where u = dlog 2 me. The size of the sum-of-products expressions (SOPs) depends on the encoding method of the outputs. For some class of functions, the optimal encoding produces SOPs with O(n) products, while the worst encoding produces SOPs with O(2 n ) products. We formulate encoding problem and show a heuristic optimization method. Experimental results using standard benchmark functions show the usefulness of the method. Index term: Multiple-output function, encoding problem, multiple-valued logic, TDM, SOP, characteristic function. 1.

Many modern FPGAs use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. Since permutations and negation of signals are virtually costless operations in FPGAs, it is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have only recently been considered for application in FPGAs. In this paper we propose a class of ULMs useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on BDD description of logic functions. We give an explicit construction of a 3-input LUT replacement that requires only 5 programming bits, which is the optimum for such ULMs. A realistic size 4-input LUT replacement is obtained which uses 13 programming bits. Such logic blocks are especially important when FPGAs are used in a reconfigurable manner, because they can...

This paper investigates the relationship between multi-cycle false paths and the testability of sequential circuits. We show that removal of multi-cycle false paths (either by circuit restructuring or by proper state encoding) improves circuit testability, but not as significantly as one would expect. We demonstrate the inability of current structure-based scan register selection techniques to select the minimum possible set of registers for high fault coverage. We then propose a novel and efficient way to exploit the causes of multi-cycle false paths to make a judicious choice of registers for maximum possible testability. Our technique is based on the analysis of the circuit behaviour and its state encoding. It is shown that this approach results in the selection of minumum possible scan register set for maximum possible fault coverage. 1 1 Introduction Over the years, sequential redundancy identification and removal has been the subject of intensive investigation. Identifying uni...

This paper presents Metamorphosis 1 -- a novel technique for optimal state assignment targeting multi-level logic implementations. We present a new formulation and synthesis techniques for the state assignment problem based on controlled retiming and re-encoding of a symbolically represented finite state machine (FSM) represented initially with a one-hot code. Metamorphosis is a new design paradigm that integrates the structural and behavioral design methodologies in a synergistic fashion and leverages the additional degrees of freedom to the synthesis of optimal FSM. The proposed technique differs drastically from previous approaches in that the encoding process is guided directly by the cost function (optimization criterion) rather than speculative estimates of the encoding heuristics on the final design cost. We present efficient encoding algorithms for both unconstrained and bit-constrained encoding problems. Another novel feature of Metamorphosis is that it permits the explora...

In this paper we present a technique to remove multi-cycle false paths from a sequential circuit by the encoding of its states. Based on behavioral level analysis, we derive the necessary and sufficient condition for the encoding of FSM to obtain a false path free implementation. This condition requires the satisfaction of false path dichotomies obtained from symbolic output and next state equations of the machine. The presented approach can significantly impact the multi-cycle false path removal techniques, traditionally applied to gate-level circuits. 1 Introduction The problem of false paths in logic circuits has been studied extensively in recent years (e.g. [8], [5], [2], [9]). False path in the circuit is a path that is never exercised during the operation of the circuit due to the circuit functionality and/or delay values of the circuit components. We shall differentiate between false paths in combinational circuits and false paths in sequential circuits. False paths in combin...

complex designs, typically to provide a path for routing operands to operations and operation results to destination registers. During RTL synthesis, multiplexers are used for realizing ifthen -else and case statements in the RTL design description. In this paper, we describe a new heuristic algorithm for synthesizing efficient multiplexers consisting of a tree of multiplexer components from a library. Area minimization is our primary goal. Hence, we first generate an area-minimal implementation of a multiplexer, using multiplexer components from the library.