An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25k gate CMOS Test Chip has been designed, manufactured (5491 devices), and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs.

Our goal is to synthesize hazard-free asynchronous circuits that are testable in the very stringent hazard-free robust path-delay-fault model. From a synthesis perspective producing circuits satisfying two very stringent requirements, namely, hazard-free operation and hazard-free robust path-delay-fault-testability, poses an especially exciting challenge. In this paper we present techniques which guarantee both hazard-free operation and hazard-free robust path-delay-fault testability, at the expense of possibly adding test inputs, and give a set of heuristics which can improve hazard-free robust path-delay-fault testability without requiring such inputs. We also present a procedure that guarantees testability in the less stringent robust gate-delay-fault model. 1 Introduction In this paper we are concerned with the problem of synthesizing asynchronous sequential circuits from a high level specification, the Signal Transition Graph (STG, [3]). In [13, 12] we presented a set of algorith...

In many designs a large portion of path delay faults is not robustly testable. In this paper, we investigate testing strategies for robustly untestable faults. We show that the quality of non-robust tests may be very poor in detecting small defects caused by manufacturing process variation. We demonstrate that better quality non-robust tests can be obtained by including timing information into the process of test generation. A good non-robust test can tolerate larger timing variations on the off-inputs. We also show that not all non-robustly untestable path delay faults may be ignored in high quality delay testing. Functional sensitizable paths are non-robustly untestable but, under some faulty conditions, may degrade the performance of the circuit. However, up till now, there was no strategy for generating tests for such faults. In this paper, we present algorithms for generating high quality non-robust and functional sensitizable tests. We also devise an algorithm for generating tes...

A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC under test. The complexity of the test procedure of such a testable ASC is reduced to that of the combinational circuit. Tests for the combinational circuit and state holding elements can be derived using standard test generation techniques.

An asynchronous ARM6 microprocessor (AMULET1), designed at the University of Manchester using a twophase signalling protocol, and the latest release of the AMULET2e embedded controller, implemented using fourphase signalling, have proved the practical feasibility of the micropipeline design approach. A built-in self-test (BIST) micropipeline design based on an asynchronous BILBO register is presented in this paper. All the stage registers of the micropipeline are implemented using the proposed asynchronous BILBO register which can operate in four modes: normal operation, shift, linear feedback shift register (LFSR) and signature analyser mode. The test procedure described in this paper provides for the detection of all single stuck-at faults in the micropipeline. It is shown that delay faults in the combinational logic blocks of the BIST micropipeline can be tested by using BILBO registers of a doubled size.

Some previously published results show that in a number of combinational circuits a significant portion of long paths is neither robustly nor non-robustly testable. However, not all of those untestable paths may be ignored in delay testing. Functional sensitizable paths are robust and non-robust untestable but, under some faulty conditions, may degrade the performance of the circuit. Even though the need for testing functional sensitizable paths was recognized in previous research, up till now, there was no strategy for generating tests for them. In this paper we present an algorithm for generating high quality tests for functional sensitizable paths based on including the timing information into the process of test derivation. Our experimental results prove that the quality of delay testing increases if additional test vectors for functional sensitizable path delay faults are included. 1 Introduction The objective of delay testing is to detect timing defects which could degrade the ...

We present a performance driven generator for integer adders which has the following interesting feature: The generator is parametrized in the operands' bitlength n, the delay of the addition t n and the fault model FM. FM may in particular be chosen as the classical stuck-at fault model, the cellular fault model or the robust path delay fault model. The output of the generator is a performance oriented conditional sum type adder, i.e., an area-minimal n-bit adder of the "conditional sum type" with delay t n (if it exists) together with a small complete test set with respect to the chosen fault model FM. Keywords---Circuit design, design for testability, area-time optimal adders, multidimensional dynamic programming. I. Introduction Since 1982, various VLSI designs for fast addition have been proposed [1], [2]. The delays of the adders presented are optimal from the asymptotic point of view. However, the actual optimal structure of a realistic adder depends on the cell library use...

It has been shown earlier that, if we restrict to unate gate network (UGN) realizations, there exist universal test sets for boolean functions. Such a test set only depends on the function f , and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper we prove that these universal test sets are much more powerful than implied by the above results: They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations, comes from the fact that we do not argue the correctness of individual paths, but complete path systems. Keywords--- Delay test, unate gate networks, universal test sets, design for testability. I. Introduction T HE development of VLSI systems is driven by the demand for higher scale ...

Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead to functional failures. Therefore, dynamic fault models like the Path Delay Fault Model (PDFM) have become more important in the last years. At the same time, classical algorithms for test pattern generation reach their limits due to the steadily increasing complexity of modern circuits. In this work, a SAT-based approach to calculate robust and non-robust test patterns for Path Delay Faults (PDF) is presented. In contrast to previous approaches, the sequential behavior of a circuit is modeled adequately. Moreover, tri-state elements and environment constraints that occur in industrial practice can be handled. The encoding to apply a Boolean SAT solver for this problem is motivated and explained in detail. Experimental results for large industrial circuits show the efficiency of this approach. 1.

In this paper we explore the test complexity of the adder function with respect to the robust path delay fault model. A lower bound of# n 2 # for the cardinality of a complete test set for a combinational n-bit adder is proven. This result is valid for any adder design known until now. In addition we present a fast O# p n#-time adder that is fully robust path delay fault testable with a test set of size ##n 2 #. 1 Introduction Even if chips are correctly designed, a non negligible fraction of them will havephysical defects caused by imperfections occurring during the manufacturing process #e.g., open connections induced by dust particles #. Therefore, there has to be a test phase in which `production' veri#cation is performed, i.e., in which the `good' chips are sorted from the `bad' ones. For a detailed treatment of the topic see #2#. Due to the variety of possible defects restrictions on a subset of the possible faults are necessary; these simplifying assumptions based on exp...