Results 1  10
of
11
Composite Model Checking: Verification with TypeSpecific Symbolic Representations
 ACM Transactions on Software Engineering and Methodology
, 2000
"... In recent years, there has been a surge of progress in automated verification methods based on state exploration. In areas like hardware design, these technologies are rapidly augmenting key phases of testing and validation. To date, one of the most successful of these methods has been symbolic mode ..."
Abstract

Cited by 30 (7 self)
 Add to MetaCart
(Show Context)
In recent years, there has been a surge of progress in automated verification methods based on state exploration. In areas like hardware design, these technologies are rapidly augmenting key phases of testing and validation. To date, one of the most successful of these methods has been symbolic model checking, in which large finitestate machines are encoded into compact data structures such as binary decision diagrams (BDDs)  and are then checked for safety and liveness properties. However, these techniques have not realized the same success on software systems. One limitation is their inability to deal with infinitestate programs  even those with a single unbounded integer. A second problem is that of finding efficient representations for various variable types. We recently proposed a model checker for integerbased systems that uses arithmetic constraints as the underlying state representation. While this approach easily verified some subtle, infinitestate concurrency problems...
Algorithms For Synthesis And Verification Of Timed Circuits And Systems
, 1999
"... In order to increase performance, circuit designers are beginning to move away from traditional, synchronous designs based on static logic. Recent design examples have shown that significant performance gains are realized when aggressive circuit styles are used. Circuit correctness in these aggressi ..."
Abstract

Cited by 11 (2 self)
 Add to MetaCart
(Show Context)
In order to increase performance, circuit designers are beginning to move away from traditional, synchronous designs based on static logic. Recent design examples have shown that significant performance gains are realized when aggressive circuit styles are used. Circuit correctness in these aggressive circuit styles is highly timing dependent, and in industry they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms to explore the reachable state space of the circuit under the timing constraints are necessary. This thesis presents a new specification method for timed circuits, timed event/level (TEL) structures, and new algorithms for exploring a timed state space. The TEL structure specification allows the designer to specify behavior controlled by signal transitions, which is best for representing sequencing, and behavior controlled by signal levels, which is best for representing gate level circuits. This thesis also...
Using MTBDDs for Discrete Timed Symbolic Model Checking
 MultipleValued Logic – An International Journal
, 1997
"... The verification of timing properties is an important task in the validation process of embedded and real time systems. Temporal logic model checking is one of the most successful techniques as it allows the complete automation of the verification. In this paper, we present a new approach to symboli ..."
Abstract

Cited by 6 (3 self)
 Add to MetaCart
The verification of timing properties is an important task in the validation process of embedded and real time systems. Temporal logic model checking is one of the most successful techniques as it allows the complete automation of the verification. In this paper, we present a new approach to symbolic QCTL (Quantitative CTL) model checking. In contrast to previous approaches we use an intuitive QCTL semantics, provide an efficient model representation and the new algorithms require less iteration steps compared to translating the QCTL problem into CTL and using standard CTL model checking techniques. The new model checking algorithm is based on a MTBDD representation. Some experimental results show the efficiency of the new approach.
Partial Order Control and Optimal Control of Discrete Event Systems Modeled as Polynomial Dynamical Systems over Galois Fields
, 1997
"... In this paper, we propose computational methods for the synthesis of controllers for discrete event systems modeled by polynomial dynamical systems over finite Galois field. The control objectives are specied as order relations to be checked and as minimization of a given cost function over the stat ..."
Abstract

Cited by 5 (1 self)
 Add to MetaCart
In this paper, we propose computational methods for the synthesis of controllers for discrete event systems modeled by polynomial dynamical systems over finite Galois field. The control objectives are specied as order relations to be checked and as minimization of a given cost function over the states through the trajectories of the system. The control objectives are then synthesized using algebraic tools such as ideals, varieties and morphisms. The applications of these methods to the safety specification of a power transformer station controller is finally presented.
Model Checking with Edgevalued Decision Diagrams
 in Proceedings of the Second NASA Formal Methods Symposium (NFM 2010), NASA/CP2010216215. NASA
, 2010
"... Abstract. We describe an algebra of EdgeValued Decision Diagrams (EVMDDs) to encode arithmetic functions and its implementation in a model checking library along with stateoftheart algorithms for building the transition relation and the state space of discrete state systems. We provide efficien ..."
Abstract

Cited by 4 (0 self)
 Add to MetaCart
(Show Context)
Abstract. We describe an algebra of EdgeValued Decision Diagrams (EVMDDs) to encode arithmetic functions and its implementation in a model checking library along with stateoftheart algorithms for building the transition relation and the state space of discrete state systems. We provide efficient algorithms for manipulating EVMDDs and give upper bounds of the theoretical time complexity of these algorithms for all basic arithmetic and relational operators. We also demonstrate that the time complexity of the generic recursive algorithm for applying a binary operator on EVMDDs is no worse than that of MultiTerminal Decision Diagrams. We have implemented a new symbolic model checker with the intention to represent in one formalism the best techniques available at the moment across a spectrum of existing tools: EVMDDs for encoding arithmetic expressions, identityreduced MDDs for representing the transition relation, and the saturation algorithm for reachability analysis. We compare our new symbolic model checking EVMDD library with the widely used CUDD package and show that, in many cases, our tool is several orders of magnitude faster than CUDD.
Timed circuit synthesis using implicit methods
 in 12th VLSI Design Conference
, 1999
"... The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification. This information is used throughout the synthesis procedure to op ..."
Abstract

Cited by 4 (3 self)
 Add to MetaCart
(Show Context)
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification. This information is used throughout the synthesis procedure to optimize the design. In order to synthesize a timed circuit, it is necessary to explore the timed state space of the specification. The memory required to store the timed state space of a complex specification can be prohibitive for large designs when explicit representation methods are used. This paper describes the application of BDDs and MTBDDs to the representation of timed state spaces and the synthesis of timed circuits. These implicit techniques significantly improve the memory efficiency of timed state space exploration and allow more complex designs to be synthesized. Implicit methods also allow the derivation of solution spaces containing all valid solutions to the synthesis problem facilitating subsequent optimization and technology mapping steps. 1.
Implicit Methods For Timed Circuit Synthesis
, 1998
"... The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification. This information is used throughout the synthesis procedure to op ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification. This information is used throughout the synthesis procedure to optimize the design. In order to synthesize a timed circuit, it is necessary to explore the timed state space of the specification. The memory required to store the timed state space of a complex specification can be prohibitive for large designs when explicit representation methods are used. This thesis describes the application of BDDs and MTBDDs to the representation of timed state spaces and the synthesis of timed circuits. These implicit techniques significantly improve the memory efficiency of timed state space exploration and allow more complex designs to be synthesized.
Manipulation Algorithms for K*BMDs
 In Proc. Tools and Algorithms for the Construction and Analysys of Systems
, 1997
"... Bitlevel and wordlevel based Decision Diagrams (DDs) have led to significant advances in the area of Computer Aided Design (CAD). Recently, a new data structure for the wordlevel, called Kronecker Multiplicative BMDs (K*BMDs), has been presented. We study manipulation algorithms for K*BMDs: Using ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
(Show Context)
Bitlevel and wordlevel based Decision Diagrams (DDs) have led to significant advances in the area of Computer Aided Design (CAD). Recently, a new data structure for the wordlevel, called Kronecker Multiplicative BMDs (K*BMDs), has been presented. We study manipulation algorithms for K*BMDs: Using K*BMDs it is possible to represent functions efficiently, that have a good wordlevel description (like multipliers). On the the other hand K*BMDs are also applicable to verification problems at the bitlevel. We clarify the relation between bit and wordlevel representation which is of importance in particular in the context of verification. Experiments show that *BMDs are not wellsuited for the bitlevel. On the other hand OBDDs are not applicable on the wordlevel. We present algorithms that allow to dynamically switch between bitlevel and wordlevel. We discuss a method for changing the decomposition type and variable order. First experiments demonstrate the efficiency...
i Table of Contents
, 2000
"... This publication was supported through Grant #98CKWXK052 from the Office of CommunityOriented Policing Services, U.S. Department of Justice. The opinions expressed herein are the ..."
Abstract
 Add to MetaCart
(Show Context)
This publication was supported through Grant #98CKWXK052 from the Office of CommunityOriented Policing Services, U.S. Department of Justice. The opinions expressed herein are the
Model Checking with Edge Valued Decision Diagrams
"... We describe an algebra of EdgeValued Decision Diagrams (EVMDDs) to encode arithmetic functions and its implementation in a model checking library. We provide efficient algorithms for manipulating EVMDDs and review the theoretical time complexity of these algorithms for all basic arithmetic and rela ..."
Abstract
 Add to MetaCart
(Show Context)
We describe an algebra of EdgeValued Decision Diagrams (EVMDDs) to encode arithmetic functions and its implementation in a model checking library. We provide efficient algorithms for manipulating EVMDDs and review the theoretical time complexity of these algorithms for all basic arithmetic and relational operators. We also demonstrate that the time complexity of the generic recursive algorithm for applying a binary operator on EVMDDs is no worse than that of MultiTerminal Decision Diagrams. We have implemented a new symbolic model checker with the intention to represent in one formalism the best techniques available at the moment across a spectrum of existing tools. Compared to the CUDD package, our tool is several orders of magnitude faster. 1