Abstruet-The problem of allocating network resources to the users of an integrated services network is investigated in the context of rate-based flow control. The network is assumed to be a virtual circuiq comection-based packet network. We show that the use of Generalized processor Sharing (GPS), when combined with Leaky Bucket admission control, allows the network to make a wide range of worst-case performance guarantees on throughput and delay. The scheme is flexible in that d~erent users may be given widely different performance guarantees, and is efilcient in that each of the servers is work conserving. We present a practicat packet-by-packet service discipline, PGPS (first proposed by Deme5 Shenker, and Keshav [7] under the name of Weighted Fair Queueing), that closely approximates GPS. This altows us to relate ressdta for GPS to the packet-bypacket scheme in a precise manner. In this paper, the performance of a single-server GPS system is analyzed exactty from the standpoint of worst-case packet delay and burstiness when the sources are constrained by leaky buckets. The worst-case sewdon backlogs are also determined. In the sequel to this paper, these results are extended to arbitrary topology networks with multiple nodes. I.

Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a prototype switch for an arbitrary topology point-to-point network with link speeds of up to one gigabit per second. The switch deals in fixed-length ATM-style cells, which it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram traffic. In addition, it supports real-time traffic by providing bandwidth reservations with guaranteed latency bounds. The key to the switch's operation is a technique called parallel iterative matching, which can quickly identify a set of conflict-free cells for transmission in a time slot. Bandwidth reservations are accommodated in the switch by building a fixed schedule for transporting cells from reserved flows across the switch; parallel iterative matching can fill unused slots with datagram traffic. Finally, we note that pa...

There is considerable interest in the provision of guaranteed-rate services for IP and ATM networks. Simultaneously, bandwidth demands make input-bu#ered architectures attractive, and in some cases, necessary. In this paper, we consider the problem of how to support guaranteed-rate services in a single-stage, input-bu#ered switch suitable for a LAN switch, an ATM switch or an IP router. Such a switchmust be feasible at high transmission speeds, o#ering both guaranteed-rate performance for CBR channels #e.g. for real-time connections#and beste #ort services for traditional data tra#c. We consider a switch scheduling mechanism that employs idling hierarchical roundrobin #HRR# scheduling and fabric arbitration at the connectionlevel for guaranteed-rate service using the Slepian-Duguid algorithm. The switch uses cell level arbitration for best-e#ort service. This overall switchscheduling mechanism is a variation of DEC's AN2 design #2#. I.

In this paper, we giveanoverview of the basic design principles and trade-o#s of output-bu#erATM switching. Outputbu #er switches give optimal performance in terms of o#ering bandwidth guarantees to individual #ows. Bandwidth scheduling and memory bandwidth requirements are also described. I.

Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a prototype switch for an arbitrary topology point-to-point network with link speeds of up to one gigabit per second. The switch deals in fixed-length ATM-style cells, which it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram traffic. In addition, it supports real-time traffic byproviding bandwidth reservations with guaranteed latency bounds. The key to the switch's operation is a technique called parallel iterative matching, which can quickly identify a set of conflict-free cells for transmission in a time slot.

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