The role of automatic formal protocol verification in hardware design is considered. Principles are identified that maximize the benefits of protocol verification while minimizing the labor and computation required. A new protocol description language and verifier (both called Mur') are described, along with experiences in applying them to two industrial protocols that were developed as part of hardware designs.

In simulation-based verification users are faced with the challenge of maximizing test coverage while minimizing testing costs. Sophisticated techniques are used to generate clever test cases and to determine the quality attained by the tests. The latter activity, which is essential for locating areas of the design that need to have more tests, is called test coverage analysis.

I hereby declare that I am the sole author of this thesis. I authorize the University of Waterloo to lend thesis to other institutions or individuals for the purpose of scholarly research. B.R. Pekilis I further authorize the University of Waterloo to reproduce this thesis by photocopying or by any other means, in total or in part, at the request of others institution or individuals for the pur-pose of scholarly research. B.R. Pekilis ii The University of Waterloo requires the signatures of all persons using or photocopying this thesis. Please sign below, and give address and date. iii The focus of the research presented in this thesis is on session-oriented, soft real-time systems whose behavior is specified using the ITU Specification and Description Language