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Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures
- In Proc. DSN
, 2006
"... Abstract—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the high availability required for these tasks, it is necessary to incorporate mechanisms for error detection and recov ..."
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Cited by 11 (5 self)
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Abstract—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the high availability required for these tasks, it is necessary to incorporate mechanisms for error detection and recovery. A correct operation of the memory system is defined by the memory consistency model. Errors can therefore be detected by checking if the observed memory system behavior deviates from the specified consistency model. Based on recent work, we design a framework for the dynamic verification of memory consistency (DVMC). The framework consists of mechanisms to dynamically verify three invariants that are proven to guarantee that a specified memory consistency model is obeyed. We describe an implementation of the framework for the SPARCv9 architecture, and we experimentally evaluate its performance by using full-system simulation of commercial workloads. Index Terms—Reliability, fault tolerance, multiprocessors, multithreaded processors. Ç
Model checking a cache coherence protocol for a Java DSM implementation
- In Proceedings FMPPTA’03
, 2003
"... Jackal is a fine-grained distributed shared memory implementation of the Java programming language. It aims to implement Java’s memory model and allows multithreaded Java programs to run unmodified on a distributed memory system. It employs a multiple-writer cache coherence protocol. In this paper, ..."
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Cited by 9 (0 self)
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Jackal is a fine-grained distributed shared memory implementation of the Java programming language. It aims to implement Java’s memory model and allows multithreaded Java programs to run unmodified on a distributed memory system. It employs a multiple-writer cache coherence protocol. In this paper, we report on our analysis of this protocol. We present its formal specification in µCRL, and discuss the abstractions that were made to avoid state explosion. Requirements were formulated and model checked with respect to several configurations. Our analysis revealed two errors in the implementation. Key words: formal specification, model checking, cache coherence protocols, Java memory model, µCRL
Abstraction Techniques for Parameterized Verification
, 2006
"... not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the sponsoring institutions, the U.S. Government, or any other entity. ..."
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Cited by 1 (0 self)
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not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the sponsoring institutions, the U.S. Government, or any other entity.

