Cut enumeration is a common approach used in a number of FPGA synthesis and mapping algorithms for consideration of various possible LUT implementations at each node in a circuit. Such an approach is very general and flexible, but often suffers high computational complexity and poor scalability. In this paper, we develop several efficient and effective techniques on cut enumeration, ranking and pruning. These techniques lead to much better runtime and scalability of the cut-enumeration based algorithms; they can also be used to compute a tight lower-bound on the size of an area-minimum mapping solution. For area-oriented FPGA mapping, experimental results show that the new techniques lead to over 160X speed-up over the original optimal duplication-free mapping algorithm, achieve mapping solutions with 5-21% smaller area for heterogeneous FPGAs compared to those by Chortle-crf [6], MIS-pga-new [9], and TOS-TUM [4], yet with over 100X speed-up over MIS-pganew [9] and TOS-TUM [4]. 1 Intr...

Abstract — This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effective heuristics are presented to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good ” candidates for the minimization of the circuit. A main advantage of the proposed approach is that it operates directly on the structural netlist description of the circuit so that the technical consequences of the performed transformations can be evaluated in an easy way, permitting better control of the optimization process with respect to the specific goals of the designer. Therefore, the presented technique can serve as a basis for optimization techniques targeting nonconventional design goals. This has already been shown for random pattern testability [11] and low-power consumption [28]. This paper only considers area minimization, and our experimental results show that the method presented is competitive with conventional technologyindependent minimization techniques. For many benchmark circuits, our tool Hannover implication tool based on learning (HANNIBAL) achieves the best minimization results published to date. Furthermore, the optimization approach presented is shown to be useful in formal verification. Experimental results show that our optimization-based verification technique works robustly for practical verification problems on industrial designs. Index Terms—ATPG, implication analysis, logic synthesis, logic verification, miter, permissible function, recursive learning, redundancy elimination, transduction. I.

This paper presents a system for disjoint decompositions of logic functions with many inputs. It is a combination of three different methods: 1) Disjoint decompositions with a few bound set variables; 2) Disjoint bi-decompositions; and 3) Decompositions using Jacobian. 1) and 2) are quick, but find only limited classes of decompositions, while 3) finds all disjoint decompositions by spending more time. Weshow the results of decompositions for more than four thousand functions. We also define a new class of functions: Completely bi-decomposable functions. Experimental results show that many practical logic functions have disjoint decompositions and some are completely bi-decomposable functions. I Introduction In general, an n-variable function f requires about 2 n =n gates [23]. Suppose that the function f can be decomposed into twonetworks as shown in Fig. 1.1. Let the numbers of inputs for the network H and G be n 1 and n 2 + 1, respectively, where n 1 + n 2 = n. Then, H and ...

This paper shows a method to decompose a given multipleoutput circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represent a multiple-output function. Many benchmark functions were realized by LUT cascades with intermediate outputs. Especially, adders and a binary to BCD converter were successfully designed. Comparison with FPGAs is also presented.

In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the mapping solutions computed by a depth-optimal mapper have minimum depth. We present several theoretical results: (1) any further decomposition of a K-bounded network will lead to an optimal mapping depth smaller than or equal to that of the original network, regardless of the decomposition algorithm used, and (2) the problem of gate decomposition for depth-optimal technology mapping is NP-hard for fanin-unbounded networks when K ³ 3 and remains NP-hard for K-bounded networks when K ³ 5. We propose a novel gate decomposition algorithm, named DOGMA, which combines level-driven node packing technique (Chortle-d) and the network flow based optimal labeling technique (FlowMap) for depth-optimal technology mapping. Experimental results show that the networks produced by DOGMA allow depth-optimal technology mappers to improve the mapping solutions by up to 11% in depth and up to 3...

In this paper, we present new Boolean matching methods for lookup table (LUT)-based programmable logic blocks (PLBs) and their applications to PLB architecture evaluations and field programmable gate array (FPGA) technology mapping. Our Boolean matching methods, which are based on functional decomposition operations, can characterize functions for complex PLBs consisting of multiple LUTs (possibly of different sizes) such as Xilinx XC4K CLBs. With these techniques, we conducted quantitative evaluation of four PLB architectures on their functional capabilities. Architecture evaluation results show that the XC4K CLB can implement 98% of six-input and 88% of seven-input functions extracted from MCNC benchmarks, while a simplified PLB architecture is more cost effective in terms of function implementation per LUT bit. Finally, we proposed new technology mapping algorithms that integrate Boolean matching and functional decomposition operations for depth minimization. Technology mapping results show that our PLB mapping approach achieves 12% smaller depth or 15% smaller area in XC5200 FPGAs and 18% smaller depth in XC4K FPGAs, compared to conventional LUT mapping approaches.

FPGA-based systems are a significant area of computing, providing a high-performance implementation substrate for many different applications. However, the key to harnessing their power for most domains is developing mapping tools for automatically transforming a circuit or algorithm into a configuration for the system. In this paper we review the current state-of-the-art in mapping tools for FPGA-based systems, including single-chip and multi-chip mapping algorithms for FPGAs, software support for reconfigurable computing, and tools for run-time reconfigurability. We also discuss the challenges for the future, pointing out where development is still needed to let reconfigurable systems achieve all of their promise. 1.0 Introduction Reconfigurable computing is becoming a powerful methodology for achieving high-performance implementations of many applications. By mapping applications into FPGA hardware resources, extremely efficient computations can be performed. In [Hauck98] w...

One of the crucial problems multi-level logic synthesis techniques for multi-output boolean functions f = (f 1 ; : : : ; fm ) : f0; 1g n ! f0; 1g m have to deal with is finding sublogic which can be shared by different outputs, i.e., finding boolean functions ff = (ff 1 ; : : : ; ff h ) : f0; 1g p ! f0; 1g h which can be used as common sublogic of good realizations of f1 ; : : : ; fm . In this paper we present an efficient robdd based implementation of this Common Decomposition Functions Problem (cdf). Formally, cdf is defined as follows: Given m boolean functions f1 ; : : : ; fm : f0; 1g n ! f0; 1g, and two natural numbers p and h, find h boolean functions ff 1 ; : : : ; ff h : f0; 1g p ! f0; 1g such that 81 k m there is a decomposition of fk of the form fk (x1 ; : : : ; xn ) = g (k) (ff 1 (x1 ; : : : ; xp ); : : : ; ff h (x1 ; : : : ; xp ); ff (k) h+1 (x 1 ; : : : ; xp ); : : : ; ff (k) r k (x 1 ; : : : ; xp ); xp+1 ; : : : ; xn ) using a minimal number rk of...

In this paper, we present a new algorithm, named TurboSYN, for FPGA synthesis with retiming and pipelining to minimize the clock period for sequential circuits. For a target clock period, since pipelining can eliminate all critical I/O paths, but not critical loops, we concentrate on FPGA synthesis to eliminate the critical loops. We combine the combinational functional decomposition technique with retiming to perform the sequential functional decomposition, and incorporate it in the label computation of TurboMap [CoWu96] to eliminate all critical loops. The results show a significant improvement over the state-of-the-art FPGA mapping and resynthesis algorithms (1:7 ¸ 2 times reduction on the clock period). Moreover, we develop a novel approach for positive loop detection which leads to over 10¸50 times speedup of the algorithm. As a result, TurboSYN can optimize sequential circuits of over 10 4 gates and 10 3 flipflops in reasonable time. 1 Introduction The FPGA synthesis and te...

Technology mapping problems arize in logic synthesis systems, when the gap between a synthesized boolean network and the implementation of that network within a given target technology has to be bridged. This paper presents a modular, versatile technology mapping system that supports many different target technologies. Guided by a complexity analysis of the problem, we develop a variety of efficient, exact or heuristic methods for technology driven network clustering. Depending on the target technology and optimization methods and goals, different subnetworks must be provided as candidates for clustering. Methods to achieve this are also included. We conclude with experimental results we obtained with several configurations of the system for different target technologies.