This paper discusses the theoretical concepts underlying a project at Rice University to develop an automatic translator, called PFC (for Parallel FORTRAN Converter), from FORTRAN to FORTRAN 8x. The Rice project, based initially upon the research of Kuck and others at the University of Illinois [6, 17-21, 24, 32, 36], is a continuation of work begun while on leave at IBM Research in Yorktown Heights, N.Y. Our first implementation was based on the Illinois PARAFRASE compiler [20, 36], but the current version is a completely new program (although it performs many of the same transformations as PARAFRASE). Other projects that have influenced our work are the Texas Instruments ASC compiler [9, 33], the Cray-1 FORTRAN compiler [15], and the Massachusetts Computer Associates Vectorizer [22, 25]. The paper is organized into seven sections. Section 2 introduces FORTRAN 8x and gives examples of its use. Section 3 presents an overview of the translation process along with an extended translation example. Section 4 develops the concept of interstatement dependence and shows how it can be applied to the problem of vectorization. Loop carried dependence and loop independent dependence are introduced in this section to extend dependence to multiple statements and multiple loops. Section 5 develops dependence-based algorithms for code generation and transformations for enhancing the parallelism of a statement. Section 6 describes a method for extending the power of data dependence to control statements by the process of IF conversion. Finally, Section 7 details the current state of PFC and our plans for its continued development

We present an algorithm to generate small Büchi automata for LTL formulae. We describe a heuristic approach consisting of three phases: rewriting of the formula, an optimized translation procedure, and simplification of the resulting automaton. We present a translation procedure that is optimal within a certain class of translation procedures. The simplification algorithm can be used for Buchi automata in general. It reduces the number of states and transitions, as well as the number and size of the accepting sets---possibly reducing the strength of the resulting automaton. This leads to more efficient model checking of lineartime logic formulae. We compare our method to previous work, and show that it is significantly more efficient for both random formulae, and formulae in common use and from the literature.

Abstract: MINI is a heuristic logic minimization technique for many-variable problems. It accepts as input a Boolean logic specification expressed as an input-output table, thus avoiding a long list of minterms. It seeks a minimal implicant solution, without generating all prime implicants, which can be converted to prime implicants if desired. New and effective subprocesses, such as expanding, reshaping, and removing redundancy from cubes, are iterated until there is no further reduction in the solution. The process is general in that it can minimize both conventional logic and logic functions of multi-valued variables.

In this paper we describe an interior point mathematical programming approach to inductive inference. We list several versions of this problem and study in detail the formulation based on hidden Boolean logic. We consider the problem of identifying a hidden Boolean function F : f0; 1g n ! f0; 1g using outputs obtained by applying a limited number of random inputs to the hidden function. Given this input-output sample, we give a method to synthesize a Boolean function that describes the sample. We pose the Boolean Function Synthesis Problem as a particular type of Satisfiability Problem. The Satisfiability Problem is translated into an integer programming feasibility problem, that is solved with an interior point algorithm for integer programming. A similar integer programming implementation has been used in a previous study to solve randomly generated instances of the Satisfiability Problem. In this paper we introduce a new variant of this algorithm, where the Riemannian metric used...

We prove that the Minimum Equivalent DNF problem is \Sigma p 2 -complete, resolving a conjecture due to Stockmeyer. The proof involves as an intermediate step a variant of a related problem in logic minimization, namely, that of finding the shortest implicant of a Boolean function. We also obtain certain results concerning the complexity of the Shortest Implicant problem that may be of independent interest. When the input is a formula, the Shortest Implicant problem is \Sigma p 2 - complete, and \Sigma p 2 -hard to approximate to within an n 1=2\Gammaffl factor. When the input is a circuit, approximation is \Sigma p 2 - hard to within an n 1\Gammaffl factor. However, when the input is a DNF formula, the Shortest Implicant problem cannot be \Sigma p 2 -complete unless \Sigma p 2 = NP[log 2 n] NP . 1. Introduction Two-level (DNF) logic minimization is a central practical problem in logic synthesis and also one of the more natural problems in the polynomial hierarchy....

Unate and binate covering problems are a special class of general integer linear programming problems with which several problems in logic synthesis, such as two-level logic minimization and technology mapping, are formulated. Previous branch-and-bound methods for exactly solving these problems use lower-bounding techniques based on finding maximal independent sets. In this paper we examine lowerbounding techniques based on linear programming relaxation (LPR) for the binate covering problem. We show that a combination of traditional reductions (essentiality and dominance) and incremental computation of LPR-based lower bounds can exactly solve difficult covering problems orders of magnitude faster than traditional methods. Keywords---Covering problems, integer linear programming I. INTRODUCTION Covering problems (unate and binate) are important combinatorial optimization problems with which several problems in logic synthesis (such as two-level logic minimization [12], state minimizati...

We present a new algorithm for exact two-level logic optimization. We represent a set of primes by the cube of their intersection. Therefore, the unique set of sets of primes which forms the covering problem can be implicitly represented by a set of cubeswhich forms a minimum canonical cover. We obtain the minimum canonical cover starting from any initial cover and then derive the table covering problem. The method is effective; it improves on the runtime and memory usage of ESPRESSO-EXACT by average factors of 1.78 and 1.2x respectively on the 114 of 134 benchmark examples that could be completed by ESPRESSO-EXACT. Of the remaining 20 hard problems, we solve 14 exactly. For 3 of the remaining 6 we derive the covering table but the covering problem could not be solved exactly. The remaining 3 remains intractable for the moment. This research supported by Fujitsu Research y Department of Electrical Engineering and Computer Sciences, University of California Berkeley 1 Introduction...

Mostly, papers on problem-solving methods focus on the description of reasoning strategies and discuss their underlying assumptions as a side aspect. We take a complementary point of view and focus on these underlying assumptions as they play three important roles: first, assumptions are necessary to characterise the precise competence of a problem-solving method in terms of the tasks that can be solved by it, and in terms of the domain knowledge that is required by it. Second, assumptions are necessary to enable tractable problem solving for complex problems. Third, assumptions are necessary for appropriate interaction of the problem solver with its environment. Their introduction and refinement can be used to develop new problem-solving methods, or to adapt existing ones according to task and domain-specific circumstances of a given application. For this purpose, one requires a framework for dealing with these assumptions. This paper makes a step in this direction by sum...

In this paper we describe a low-power infra-red communications receiver chip designed using asynchronous techniques. We focus on aspects that were difficult to implement asynchronously, and contrast our techniques with synchronous ones, where possible. We also detail the methodology used to design the chip, and the asynchronous toolset that was created to support it. 1. Introduction Asynchronous logic design is currently receiving much attention as an alternative to traditional synchronous design [2], [5], [6], [7], [8], [9], [13], [14]. Asynchronous designs do not use a global clock, simplifying global chip routing and eliminating problems due to clock skew. Furthermore, a large portion of a synchronous chip's power budget is dedicated to driving the clock, whereas elimination of the global clock in an asynchronous chip allows it to achieve near-zero standby power when quiescent. For this reason asynchronous design is particularly attractive for battery operated applications. Unfortu...

Thanks to both the rapid deployment of the Internet and advances in satellite technology, the market for broadband satellite services is poised for substantial growth in the coming decade. Current communications satellite systems have generally been designed to provide either voice or data transaction (low data rate) services through small terminals, or trunking (high data rate, or broadband) services through large terminals. However, technological advances are enabling new systems that combine broadband data rates with small terminals, thereby providing more affordable "last-mile" network access to home and small business users worldwide. In particular, two types of broadband satellite systems are under development: high-power satellites deployed at tradit...