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Reconfigurable Computing: A Survey of Systems and Software
, 2000
"... Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solu ..."
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Cited by 258 (5 self)
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Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which re-use the configurable hardware during program execution.
Operating systems for reconfigurable embedded platforms: online scheduling of realtime tasks,”
- IEEE Transactions on Computers,
, 2004
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Multitasking on FPGA Coprocessors
- IN PROCEEDINGS OF THE 10TH INTERNATIONAL WORKSHOP ON FIELD PROGRAMMABLE GATE ARRAYS (FPL
"... Multitasking on an FPGA-based processor is one possibility to explore the efficacy of reconfigurable computing. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuratio ..."
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Cited by 35 (0 self)
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Multitasking on an FPGA-based processor is one possibility to explore the efficacy of reconfigurable computing. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture allows investigating the problems of implementing realistic multitasking. This paper explores the control software required to support task switching for an application split over the host processor -- coprocessor boundary as well as the requirements and features of context saving and restoring in the FPGA coprocessor context. An FPGA coprocessor designed especially to support multitasking of such applications is described.
Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform
- In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Architectures (ERSA
, 2002
"... Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs rises a number of questions on the management of the reconfigurable resource, which leads to concepts of reconfigurable operating systems. ..."
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Cited by 26 (3 self)
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Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs rises a number of questions on the management of the reconfigurable resource, which leads to concepts of reconfigurable operating systems.
Configurable Computing: A Survey of Systems and Software
, 1999
"... Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solu ..."
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Cited by 21 (3 self)
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Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which re-use the configurable hardware during program execution. Introduction There are two primary methods in traditional computing for the execution of algorithms. The first is to use an Application Specific Integrated Circuit, or ASIC, to perform the ope...
Preemptive Multitasking on FPGAs
- Coprocessors”, Proc. 10th Int´l Conf. Field Programmable Logic and Applications
, 2000
"... In exploring the e#cacy of reconfigurable computing, one of the dimensions is the possibility for multitasking on an FPGA-based processor. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to d ..."
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Cited by 16 (1 self)
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In exploring the e#cacy of reconfigurable computing, one of the dimensions is the possibility for multitasking on an FPGA-based processor. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture enables exploring the problems of implementing realistic multitasking. 1 Introduction FPGAs for custom computing machines have shown remarkable speedups for several classes of algorithms in the past years. Reasons for high speedups can be seen in deep pipeline stages and the usage of parallelism for the algorithm execution. One ongoing field of research is the run time reconfiguration (RTR) of FPGAs. Most RTR approaches use FPGA coprocessors like Pamette or microEnable [1] as a base platform, due to the tight coupling needed for the FPGA control. RTR makes use of the reconfigurability of the FPGAs. Algorithms whi...
Memory Management to Support Multitasking on FPGA Based Systems
- In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReCon
, 2004
"... This work targets platforms, which consist beside memory and peripheral devices of FPGAs as the only computational resource. ..."
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This work targets platforms, which consist beside memory and peripheral devices of FPGAs as the only computational resource.
3-Tier Reconfiguration Model For FPGAs Using Hardwired Network on Chip
- in FPT
, 2009
"... Abstract—We envision that future Field-Programmable Gate Arrays (FPGAs) will use a Hardwired Network on Chip (HWNoC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper we present a 3-tier reconfiguration model t ..."
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Abstract—We envision that future Field-Programmable Gate Arrays (FPGAs) will use a Hardwired Network on Chip (HWNoC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper we present a 3-tier reconfiguration model that uses the HWNoC as the underlying platform to realize dynamic loading, starting, and stopping of applications. The model ensures that applications are guaranteed their required resources (LUTs, communication, memory). Resource allocation is performed globally at design time. Applications are started and stopped dynamically at run time, yet are composable, i.e. do not affect each other when they do so. Our model comprises three layers: system manager, application manager, and application. The system manager instantiates (configures) and enforces the resource allocation (LUTs, NoC connections, memories) at run time. Each application is independent, and is accompanied by an application manager that programs (starts and stops) the application, within its allocated resources (a virtual platform). We model our system in cycle-accurate transaction-level SystemC which includes bitstream loading, HWNoC and IP programming, clocking, reset, computation. directly implemented in silicon, e.g. Power PC. We define (re)configuration as the loading of new soft IPs in the FPGA by sending a bitstream to a reconfiguration region. An IP is programmed after it is configured, if necessary, which entails changing the state of its registers when it is in functional mode. A use-case is defined as a set of concurrently executing applications. I.
An efficient approach to hide the run-time reconfiguration from SW applications
- IEEE Proceedings of the 15th Field Programmable Logic and Applications (FPL). 2005. Pp
"... Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to make the reconfiguration management transparent to software applications is required in order to make easier the design with such devices. In this paper, we present an efficient approach similar to the c ..."
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Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to make the reconfiguration management transparent to software applications is required in order to make easier the design with such devices. In this paper, we present an efficient approach similar to the cache miss and the data replacement in modern computer system for the task. The main advantage is that the reconfiguration can be correctly issued without extra instructions inserted either manually by SW application programmers or automatically by compilers. The approach was validated in a real case design. In the Virtex2P20 implementation platform, the resource overhead was 2.45 % in terms of the number of LUTs. Performance is measured in cycle-accurate simulation environment. The overhead is about equal when compared with an OS-based equivalent design that uses system calls and critical section code to manage the reconfiguration. 1.
Current Trends in Resource Management of Reconfigurable Systems
"... Abstract — Considering multiple applications on a system which are executing concurrently, there should be mechanisms and policies which manage the competition for resources between them and resolve the conflicts. In a traditional system, these management activities can be summarized as storage mana ..."
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Abstract — Considering multiple applications on a system which are executing concurrently, there should be mechanisms and policies which manage the competition for resources between them and resolve the conflicts. In a traditional system, these management activities can be summarized as storage management for saving the required data and I/O management to interact with the outside world. Theoretic foundations of these activities have been fully explored in literature. In view of reconfigurable systems, additional management tasks would be imposed which include FPGA logic area allocation, placement, routing, and network on chip management. This paper presents those management activities. Index Terms — Operating systems, Reconfigurable architectures, Resource management, Scheduling
