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36
Operating systems for reconfigurable embedded platforms: online scheduling of realtime tasks,”
- IEEE Transactions on Computers,
, 2004
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A self-reconfiguring platform
- In Proceedings of Field Programmable Logic and Applications (2003
, 2003
"... Abstract. A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. This platform has been implemented on Xilinx Virtex II¦¨ § and Virtex II Pro¦© § devices. The platform’s hardware architecture has been designed ..."
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Cited by 37 (0 self)
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Abstract. A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. This platform has been implemented on Xilinx Virtex II¦¨ § and Virtex II Pro¦© § devices. The platform’s hardware architecture has been designed to be the low level configuration interface. The Xilinx Partial Reconfiguration Toolkit (XPART), the higher level of the two APIs, provides methods for reading and modifying select FPGA resources. It also provides support for relocatable partial bitstreams. The presented self-reconfiguring platform enables embedded applications to take advantage of dynamic partial reconfiguration without requiring external circuitry. 1
Networks on Chip as Hardware Components of an OS for Reconfigurable Systems
- In Proceedings of 13th International Conference on Field Programmable Logic and Applications
, 2003
"... Abstract. In complex reconfigurable SoCs, the dynamism of applications requires an efficient management of the platform. To allow run-time allocation of resources, operating systems and reconfigurable SoC platforms should be developed together. The operating system requires hardware support from the ..."
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Cited by 22 (0 self)
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Abstract. In complex reconfigurable SoCs, the dynamism of applications requires an efficient management of the platform. To allow run-time allocation of resources, operating systems and reconfigurable SoC platforms should be developed together. The operating system requires hardware support from the platform to abstract the reconfigurable resources and to provide an efficient communication layer. This paper presents our work on interconnection networks which are used as hardware support for the operating system. We show how multiple networks interface to the reconfigurable resources, allow dynamic task relocation and extend OS-control to the platform. An FPGA implementation of these networks supports the concepts we describe. 1
An Execution Model for Hardware/Software Compilation and its System-Level Realization
- Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL
"... We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then characterize the architectural and OS-level requirements of implementing the model, and demonstrate how they can be achiev ..."
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Cited by 10 (6 self)
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We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then characterize the architectural and OS-level requirements of implementing the model, and demonstrate how they can be achieved on a real hardware platform running under a full scale multi-tasking virtual protected memory operating system. Experimental measurements show the efficiency of our solution, and also prove that reconfigurable computing can be competitive with processors even for nonstreaming, pointer-chasing applications. 1.
Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems
- Proceedings of the International Conference on Engineering Reconfigurable Systems and Algorithms 2003, Las Vegas
, 2003
"... The need for flexible computational power has motivated many researchers to incorporate run-time reconfigurable logic into their architectures. Most contemporary experiments include commercial FPGA's serving as reconfigurable hardware. Unfortunately, the FPGA does not exhibit the same run-time ..."
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Cited by 9 (3 self)
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The need for flexible computational power has motivated many researchers to incorporate run-time reconfigurable logic into their architectures. Most contemporary experiments include commercial FPGA's serving as reconfigurable hardware. Unfortunately, the FPGA does not exhibit the same run-time flexibility as the Instruction Set Processor (ISP) e.g. when it comes to ease and speed of setting up a task. In addition, FPGA's tend to be less suited than traditional ISP's to accommodate control-flow dominated tasks. Obviously, it is possible to alleviate some of these issues by using a reconfiguration hierarchy (e.g. placing and configuring an ASIP or coarse grain reconfigurable block into the FPGA). This paper illustrates how our operating system transparently manages the complexity of hierarchical reconfiguration. In addition, this paper highlights the benefits and drawbacks of employing multiple hierarchical levels of configuration. As a proof of concept, we developed a filtering application on top of an in-house 16 bit microcontroller and a parameterizable filter block, both instantiated inside an FPGA.
1 Architectures and Execution Models for Hardware/Software Compilation and their System-Level Realization
"... Abstract—We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can ..."
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Cited by 7 (6 self)
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Abstract—We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. One of these is a low-latency HA-to-GPP signaling scheme with latency up to 23x times shorter than conventional approaches. Another one is a high-bandwidth shared memory interface that does not interfere with time-critical operating system functions executing on the GPP, and still makes 89 % of the physical memory bandwidth available to the HA. Finally, we show two schemes with different flexibility / performance trade-offs for running the HA in protected virtual memory scenarios. All of the techniques and their interactions are evaluated at the system level using the full-scale virtual memory variant of the Linux operating system on actual hardware.
Adaptive allocation of software and hardware real-time tasks for FPGAbased embedded systems
- In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium
, 2006
"... Operating systems for reconfigurable devices enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks running on a reconfigurable hardware device (FPGA). Furthermore, in such systems relocatable tasks can be migrated from software to hardware ..."
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Cited by 6 (2 self)
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Operating systems for reconfigurable devices enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks running on a reconfigurable hardware device (FPGA). Furthermore, in such systems relocatable tasks can be migrated from software to hardware and viceversa. The combination of high performance and predictability of hardware execution with software flexibility makes such architecture especially suitable to implement high-performance real-time embedded systems. In this work, we first discuss design and scheduling issues for relocatable tasks. We then concentrate on the on-line admission control problem. Task allocation and migration between the CPU and the reconfigurable device is discussed and sufficient feasibility tests are derived. Finally, the effectiveness of our relocation strategy is shown through a series of synthetic simulations. 1
Software-Controlled Dynamically Swappable Hardware Design in Partially Reconfigurable Systems
, 2008
"... We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the par ..."
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Cited by 6 (2 self)
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We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the partially reconfigurable logic at runtime in some intermediate state of computation and then swapped in when required to continue from that state. The context data is saved to a buffer in the wrapper at interruptible states, and then the wrapper takes care of saving the hardware context to communication memory through a peripheral bus, and later restoring the hardware context after the design is swapped in. The overheads of the hardware standardization and the wrapper in terms of additional reconfigurable logic resources and the time for context switching are small and generally acceptable. With the capability for dynamic swapping, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems so that the utilization of hardware space per unit time is increased.
Partial dynamic reconfiguration in a multifpga clustered architecture based on linux
- in Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International
, 2007
"... Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a Multi ..."
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Cited by 6 (1 self)
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Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a Multi-FPGA Clustered Architecture (MFCA). All FPGAs can be partially and dynamically reconfigured to integrate user-defined IP-Cores into the system at run-time. For the resource management and communication management we have implemented a Linux Operating System on the embedded processor that can be used to control the reconfiguration of the FPGAs by means of simple function calls. Furthermore, the Linux OS completely hides the physical infrastructure of the MFCA from user applications, offering a consistent interface to utilize partial reconfiguration. 1
FPGA-aware garbage collection in Java
- IN 2005 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL
, 2005
"... During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. This paper identifies the different levels of abstraction of hardware and software as a major culprit of this mismatch. For example, when programming in high-level object-oriented langua ..."
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Cited by 5 (1 self)
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During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. This paper identifies the different levels of abstraction of hardware and software as a major culprit of this mismatch. For example, when programming in high-level object-oriented languages like Java, one has disposal of objects, methods, memory management,... that facilitates development but these have to be largely abandoned when moving the same functionality into hardware. As a solution, this paper presents a virtual machine, based on the Jikes Research Virtual Machine, that is able to bridge the gap by providing the same capabilities to hardware components as to software components. This seamless integration is achieved by introducing an architecture and protocol that allow reconfigurable hardware and software to communicate with each other in a transparent manner i.e. no component of the design needs to be aware whether other components are implemented in hardware or in software. Further, in this paper we present a novel technique that allows reconfigurable hardware to manage dynamically allocated memory. This is achieved by allowing the hardware to hold references to objects and by modifying the garbage collector of the virtual machine to be aware of these references in hardware. We present benchmark results that show, for four different, wellknown garbage collectors and for a wide range of applications, that a hardware-aware garbage collector results in a marginal overhead and is therefore a worthwhile addition to the developer’s toolbox.
