When binding a logic network to a set of cells, a fundamental problem is recognizing whether a cell can implement a portion of the network. Boolean...

We review Binary Decision Diagrams presenting the properties and algorithms that are most relevant to their application to the verification of sequential systems.

In this paper we present a new method for Boolean matching of completely specified Boolean functions. The canonical Generalized Reed-Muller forms are used as a powerful analysis tool. Input permutation, input and output negation for matching are handled simultaneously. To reduce the search space for input correspondence, we have developed a method that can detect symmetries of any number of inputs simultaneously. Experiments on MCNC benchmark circuits are very encouraging.

Boolean matching is a powerful technique that has been used in technology mapping to overcome the limitations of structural pattern matching. The current basis for performing Boolean matching is the computation of a canonical form to represent functions that are equivalent under negation and permutation of inputs and outputs. In this paper, we first present a detailed analysis of previous techniques for Boolean matching. We then describe a novel combination of existing methods and new ideas that results in a matcher which is dramatically faster than previous work. We point out that the presented algorithm is equally relevant for detecting generalized functional symmetries, which has broad applications in logic optimization and verification.

Abstract – An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for computing the proposed canonical form is provided. The efficiency of the algorithm allows it to be applicable to large complex Boolean functions with no limitation on the number of input variables as apposed to previous approaches, which are not capable of handling functions with more than seven inputs. Generalized signatures are used to define and compute the canonical form while symmetry of variables is used to minimize the computational complexity of the algorithm. Experimental results demonstrate the efficiency and applicability of the proposed canonical form. I.

This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As a basis of the Boolean matching, we use the notion P-representative. If two functions have the same P-representative then they match. We develop a breadth-first search technique to quickly compute the P-representative. On an ordinary workstation, on the average, our method requires several microseconds to test the Boolean matching for functions with up to eight variables. This approach is promising for Boolean matching of multiplexor-based field-programmable gate arrays (FPGAs) and for library matching with many large cells. Index Terms---Boolean matching, technology mapping, variable permutation, P-equivalence. I. INTRODUCTION Boolean matching is a technique to detect the equivalence of two Boolean functions under permutation of the variables. One of the main application of Boolean matching is in cell-library...

Incremental Methods for Formal Verification and Logic Synthesis by Gitanjali Meher Swamy Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences University of California, Berkeley Professor Robert K. Brayton, Chair IC design is an iterative process; the initial specification of a design is rarely complete and correct. The designer begins with a preliminary and usually incorrect sketch (possibly from a previous generation design), and iteratively refines and corrects it. Usually, refinements are small, and there is much common information between successive design iterations. The current genre of CAD tools do not take into account this iterative nature of design. For each change made to the design, the design is re-verified and re-optimized without taking advantage of information from previous iterations. This leads to inefficient performance. In this thesis, we propose the paradigm of incremental algorithms for CAD. Incremental algorithms use information from a...

This paper presents an efficient technique for solving a Boolean matching problem in cell-library binding, where the number of cells in the library is large. As a basis of the Boolean matching, we use the notion NP-representative (NPR); two functions have the same NPR if one can be obtained from the other by a permutation and/or complementation(s) of the variables. By using a table look-up and a tree-based breadthfirst search strategy, our method quickly computes NPR for a given function. Boolean matching of the given function against the whole library is determined by checking the presence of its NPR in a hash table, which stores NPRs for all the library functions and their complements. The effectiveness of our method is demonstrated through experimental results, which shows that it is more than two orders of magnitude faster than the Hinsberger-Kolla's algorithm---the fastest Boolean matching algorithm for large libraries.

We consider the problem of detecting the equivalence of two single-output Boolean functions, considering the permutation and complementation of their inputs, complementation of outputs, and their associated don't-care sets. This is often referred to as the Boolean matching problem. Boolean matching is a verification problem, and it has important applications in logic synthesis problems such as technology-mapping [1, 2, 3]. In this paper, we present a new algorithm for solving the Boolean matching problem which is based on Boolean unification and branch-and-bound techniques. We have applied this algorithm to the task of technologymapping for cell-based designs, and experimental results show that it is an efficient and effective algorithm. Comparisons with existing Boolean matching algorithms will also be presented. 1 Introduction and Review of Previous Work In design verification, we often need to test the equivalence of two combinational circuits. If the correspondence of the inputs ...

Pattern matching algorithm is simple and fast comparing to other matching algorithms such as Boolean matching. One major drawback of the pattern matching is that there is a case where a cell needs a lot of patterns representing its logic function. That is because patterns are decomposed into 2-AND/NOT patterns to match against decomposed subject graphs. Furthermore, the conventional technology mapper does not pay much attention to relations among patterns. Each pattern is tried to match independently. In this paper, a novel pattern matching algorithm that does not require patterns to be decomposed and couple of speeding up techniques utilizing inter-relations among cells are described. These methods are very effective for large cell libraries with complex cells. Experimental results show that our methods gain matching time up to 40 times faster. 1 Introduction Pattern matching algorithm is widely used for practical technology mapping programs[1, 2]. It is simple and fast comparing to...