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... actual program performance on a 360 MHz Sun UltraSparc2 platform. Though tiling only targeted the L1 cache, we also expect indirect improvements in L2 cache performance as shown by previous research =-=[27]-=-. Cache miss rates were simulated for the 16K L1 and 2M L2 direct-mapped caches present in this architecture. To compare original and optimized performance thoroughly, we varied problem sizes over a r...

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...rs. For improving multilevel memory hierarchy performance, a new compiler technique is proposed in [28] that transforms loop nests into recursive form. However, only multilevel caches were considered =-=[22]-=-, [28] with no emphasis on TLB. It was proposed in [13] that cache and TLB performance be considered in concert to select the tile size. In this analysis, TLB and cache were assumed to be fully-set as...

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.... Much research has been performed by the compiler and algorithms community on improving memoryhierarchy performance by using techniques such as loop transformation, array padding, and cache blocking =-=[7,8,9]-=-, and we use some of these optimizations in our optimized packing algorithms. Many compilers use some of these optimizations to improve code performance. However, longer compile times and dynamic beha...

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...s overhead in the loop nest that visits the full tiles; however, the resulting code experiences significant code expansion. All the above techniques are for a single level of tiling. Rivera and Tseng =-=[29]-=- studied the effect of multiple levels of tiling for improving locality on multi-level caches. Multilevel tiled loop generation was not their focus. For simple rectangular iteration spaces, multi-leve...

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...ith poor memory performance and substantial use of indirection vectors; smg2000 is a semi-coarsening multigrid solver. mgrid and swim are stencil codes that benefit from tiling and stream prefetching =-=[25]-=-. su2cor applies a Monte-Carlo method to compute the masses of elementary particles using the Quark-Gluon theory; it is known to benefit from inter-variable padding [26]. FT is a 3D Fast Fourier Trans...

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...by an equipment grant from Intel Corporation. previous optimizations concentrate on single-level cache [8, 11, 15, 19, 23]. Multi-level caches in memory hierarchy were considered by a few researchers =-=[20, 25]-=-. However, most of these approaches target mainly the cache performance, paying less attention to the Translation Look-aside Buffer (TLB) performance. As the problem sizes become larger, the overall p...

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... (and thus multiple cache sizes), Rivera and Tseng have found that nearly all the benefits can be achieved by simply targeting the first-level cache, provided that the next level cache is much larger =-=[33]. Therefore, th-=-e discussed algorithms assume tile size selection of the first-level data cache. 15scost(h × w) = b/h +1/w good(h × w) = min(n/P, 1) ∗ w ≤ β ∗ E(no TLB misses) shape(h × w) = h ∗ w ≥ α ...

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...al solution is found, we show that after padding, the conflict miss ratio of the evaluated benchmarks is almost negligible. Besides, comparing our method with previous frameworks that address padding =-=[17, 19]-=-, it turns out that in 91% of the cases our approach yields better results. The rest of this paper is organized as follows. Section 2 presents the padding technique and its performance is evaluated in...